Author

Manish Kumar Jaiswal

Observed name: Manish K. Jaiswal

Observed institutions: City University of Hong Kong, Indian Institute of Technology Madras, ICFAI University, Dehradun, University of Hong Kong

ORCID: 0000-0002-8722-508X

Observed ORCID: 0000-0002-8722-508X

OpenAlex ID: A5080026041

PACoGen: A Hardware Posit Arithmetic Core Generator

2019 · Manish Kumar Jaiswal, Hayden K.-H. So · IEEE Access · 109

Z-TCAM: An SRAM-based Architecture for TCAM

2014 · Zahid Ullah, Manish K. Jaiswal, et al. · IEEE Transactions on Very Large Scale Integration (VLSI) Systems · 87

FPGA-Based High-Performance and Scalable Block LU Decomposition Architecture

2011 · Manish Kumar Jaiswal, Nitin Chandrachoodan · IEEE Transactions on Computers · 64

Universal number posit arithmetic generator on FPGA

2018 · Manish Kumar Jaiswal, Hayden K.-H So · Design, Automation, and Test in Europe · 55

E-TCAM: An Efficient SRAM-Based Architecture for TCAM

2014 · Zahid Ullah, Manish Kumar Jaiswal, et al. · Circuits Systems and Signal Processing · 53

UE-TCAM: An ultra efficient SRAM-based TCAM

2015 · Zahid Ullah, Manish K. Jaiswal, et al. · IEEE Region 10 Conference (TENCON) · 52

Architecture Generator for Type-3 Unum Posit Adder/Subtractor

2018 · Manish Kumar Jaiswal, Hayden K.-H So · IEEE International Symposium on Circuits and Systems proceedings · 51

FPGA Implementation of SRAM-based Ternary Content Addressable Memory

2012 · Zahid Ullah, Manish Kumar Jaiswal, et al. · 34

Area-efficient architectures for double precision multiplier on FPGA, with run-time-reconfigurable dual single precision support

2013 · Manish Kumar Jaiswal, Ray C.C. Cheung · Microelectronics Journal · 30

Fast Content Updating Algorithm for an SRAM-Based TCAM on FPGA

2017 · Farkhanda Syed, Zahid Ullah, et al. · IEEE Embedded Systems Letters · 29

DSP48E efficient floating point multiplier architectures on FPGA

2017 · Manish Kumar Jaiswal, Hayden K.-H. So · International Conference on VLSI Design and International Conference on Embedded Systems (VLSID) · 18

Unified Architecture for Double/Two-Parallel Single Precision Floating Point Adder

2014 · Manish Kumar Jaiswal, Ray C. C. Cheung, et al. · IEEE Transactions on Circuits & Systems II Express Briefs · 18

Area-Efficient Architecture for Dual-Mode Double Precision Floating Point Division

2016 · Manish Kumar Jaiswal, Hayden K.-H. So · IEEE Transactions on Circuits and Systems I Regular Papers · 15

VLSI Implementation of Double-Precision Floating-Point Multiplier Using Karatsuba Technique

2012 · Manish Kumar Jaiswal, Ray C. C. Cheung · Circuits Systems and Signal Processing · 15

Area-Efficient Architectures for Large Integer and Quadruple Precision Floating Point Multipliers

2012 · Manish Kumar Jaiswal, Ray C.C. Cheung · IEEE International Symposium on Field-Programmable Custom Computing Machines (FCCM) · 13

Dual-mode double precision / two-parallel single precision floating point multiplier architecture

2015 · Manish Kumar Jaiswal, Hayden K.-H So · IFIP/IEEE International Conference on Very Large Scale Integration · 12

Configurable Architectures for Multi-Mode Floating Point Adders

2015 · Manish Kumar Jaiswal, B. Sharat Chandra Varma, et al. · IEEE Transactions on Circuits and Systems I Regular Papers · 10

High Performance Reconfigurable Architecture for Double Precision Floating Point Division

2012 · Manish Kumar Jaiswal, Ray C. C. Cheung · Lecture notes in computer science · 9

Series Expansion based Efficient Architectures for Double Precision Floating Point Division

2014 · Manish Kumar Jaiswal, Ray C. C. Cheung, et al. · Circuits Systems and Signal Processing · 8

Taylor Series Based Architecture for Quadruple Precision Floating Point Division

2016 · Manish Kumar Jaiswal, Hayden K.-H. So · IEEE Computer Society Annual Symposium on VLSI · 7

Configurable Architecture for Double/Two-Parallel Single Precision Floating Point Division

2014 · Manish Kumar Jaiswal, Ray C.C. Cheung, et al. · IEEE Computer Society Annual Symposium on VLSI · 7

Area-Efficient FPGA Implementation of Quadruple Precision Floating Point Multiplier

2012 · Manish Kumar Jaiswal, Ray C.C. Cheung · 6

Efficient Implementation of IEEE Double Precision Floating-Point Multiplier on FPGA

2008 · Manish Kumar Jaiswal, Nitin Chandrachoodan · 6

Architecture for quadruple precision floating point division with multi-precision support

2016 · Manish Kumar Jaiswal, Hayden K.-H So · IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP) · 5

Design space explorations of Hybrid-Partitioned TCAM (HP-TCAM)

2013 · Zahid Ullah, Manish K. Jaiswal, et al. · International Conference on Field Programmable Logic and Applications (FPL) · 5

Works count: 34

Citation count: 735

H-index: 14

I10-index: 17