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D. Nee
Observed names:
D Née,
Didier Nee
Institution:
STMicroelectronics (France)
Observed institutions:
STMicroelectronics (France),
Institut des Matériaux, de Microélectronique et des Nanosciences de Provence
OpenAlex ID:
A5083402140
Temperature and drain voltage dependence of gate-induced drain leakage
2004
·
L Lopez
, P Masson
, et al.
·
Microelectronic Engineering
·
17
EEPROM memory: threshold voltage built in self diagnosis
2004
·
J.M. Portal
, H. Aziza
, et al.
·
IEEE International Test Conference (ITC)
·
12
Floating-gate EEPROM cell model based on MOS model 9
2003
·
J.M. Portal
, L. Forli
, et al.
·
IEEE International Symposium on Circuits and Systems proceedings
·
12
EEPROM Compact Model with SILC Simulation Capability
2006
·
A. Regnier
, J.M. Portal
, et al.
·
Non-Volatile Memory Technology Symposium
·
11
Test Structure for Process and Product Evaluation
2007
·
F. Rigaud
, J.M. Portal
, et al.
·
IEEE International Conference on Microelectronic Test Structures (ICMTS)
·
7
An automated methodology to diagnose geometric defect in the EEPROM cell
2003
·
J.M. Portal
, L. Forli
, et al.
·
IEEE International Test Conference (ITC)
·
4
Peripheral Circuitry Impact on LEPROM Threshold Voltage
2007
·
H. Aziza
, J.M. Portal
, et al.
·
Non-Volatile Memory Technology Symposium
·
3
Speeding up simulation time in EEPROM memory designs
2006
·
H. Aziza
, B. Delsuc
, et al.
·
International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS)
·
3
Mixed test structure for soft and hard defect detection
2008
·
F. Rigaud
, J. M. Portal
, et al.
·
IEEE International Conference on Microelectronic Test Structures (ICMTS)
·
2
A New Embedded Measurement Structure for eDRAM Capacitor
2005
·
L. Lopez
, J.M. Portal
, et al.
·
Design, Automation, and Test in Europe
·
2
PDF
Flash memory cell diagnosis: high level model
2005
·
J.M. Portal
, B. Saillet
, et al.
·
IEEE Computational Systems Bioinformatics Conference (CSB)
·
2
An automated design methodology for EEPROM cell (ADE)
2003
·
J.M. Portal
, L. Forli
, et al.
·
Records of the IEEE International Workshop on Memory Technology, Design, and Testing
·
1
Back-end soft and hard defect monitoring using a single test chip
2011
·
Fabrice Rigaud
, Jean-Michel Portal
, et al.
·
Microelectronics Reliability
Flash memory cell: parametric test data reconstruction for process monitoring
2006
·
B. Saillet
, J.M. Portal
, et al.
·
Proceedings
EEPROMCompact ModelwithSILCSimulation Capability
2006
·
A. Régnier
, J.M. Portal
, et al.
Test chip and infrastructure IP solutions to improve the back-end process during all phases from a new technology development to manufacturing
2005
·
L. Forli
, J.M. Portal
, et al.
·
International Caribbean Conference on Devices, Circuits and Systems
A low cost test vehicle for embedded DRAM capacitor: Investigation and monitoring of the process
2004
·
L. Lopez
, D. Nee
, et al.
·
IEEE International Reliability Physics Symposium proceedings
Floating-gate EEPROM cell: threshold voltage sensibility to geometry
2003
·
J.M. Portal
, L. Forli
, et al.
·
IEEE International Symposium on Circuits and Systems proceedings
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Works count:
18
Citation count:
76
H-index:
5
I10-index:
4
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