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Hidekazu Oda

Novel locally strained channel technique for high performance 55nm CMOS
2003 · K. Ota, K. Sugihara, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 98
Smallest Vth variability achieved by intrinsic silicon on thin BOX (SOTB) CMOS with single metal gate
2008 · Y. Morita, R. Tsuchiya, et al. · Symposium on VLSI Technology · 77
Ultra-low power and ultra-low voltage devices and circuits for IoT applications
2016 · T. Hiramoto, K. Takeuchi, et al. · IEEE Silicon Nanoelectronics Workshop · 34
Three-dimensional topography simulation model: etching and lithography
1990 · M. Fujinaga, N. Kotani, et al. · IEEE Transactions on Electron Devices · 30
Effect of >100< channel direction for high performance SCE immune pMOSFET with less than 0.15 μm gate length
2003 · H. Sayama, Y. Nishida, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 29
Source-to-drain breakdown voltage improvement in ultrathin-film SOI MOSFET's using a gate-overlapped LDD structure
1994 · Y. Yamaguchi, T. Iwamatsu, et al. · IEEE Transactions on Electron Devices · 26
Controllable Inverter Delay and Suppressing Vth Fluctuation Technology in Silicon on Thin BOX Featuring Dual Back-Gate Bias Architecture
2007 · Ryuta Tsuchiya, Takashi Ishigaki, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 24
Novel SOI wafer engineering using low stress and high mobility CMOSFET with >100<-channel for embedded RF/analog applications
2003 · T. Matsumoto, S. Maeda, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 23
A Perpetuum Mobile 32bit CPU with 13.4pJ/cycle, 0.14µA sleep current using Reverse Body Bias Assisted 65nm SOTB CMOS technology
2014 · Koichiro Ishibashi, Nobuyuki Sugii, et al. · IEEE Symposium in Low-Power and High-Speed Chips (COOL CHIPS) · 22
Poly/high-k/SiON gate stack and novel profile engineering dedicated for ultralow-voltage silicon-on-thin-BOX (SOTB) CMOS operation
2012 · Y. Yamamoto, H. Makiyama, et al. · Symposium on VLSI Technology · 20
Statistical Write Stability Characterization in SRAM Cells at Low Supply Voltage
2016 · Hao Qiu, Kiyoshi Takeuchi, et al. · IEEE Transactions on Electron Devices · 17
Silicon on thin BOX (SOTB) CMOS for ultralow standby power with forward-biasing performance booster
2008 · T. Ishigaki, R. Tsuchiya, et al. · European Solid-State Device Research Conference · 17
Silicon on thin BOX (SOTB) CMOS for ultralow standby power with forward-biasing performance booster
2009 · T. Ishigaki, R. Tsuchiya, et al. · Solid-State Electronics · 16
70 nm SOI-CMOS of 135 GHz f/sub max/ with dual offset-implanted source-drain extension structure for RF/analog and logic applications
2002 · T. Matsumoto, S. Maeda, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 16
Leakage current observation on irregular local PN junctions forming the tail distribution of DRAM retention characteristics, with new test structure
1998 · T. Ueno, T. Yamashita, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 15
Reduced drain current variability in fully depleted silicon-on-thin-BOX (SOTB) MOSFETs
2012 · T. Mizutani, Y. Yamamoto, et al. · IEEE Silicon Nanoelectronics Workshop · 14
Impact of random telegraph noise on write stability in Silicon-on-Thin-BOX (SOTB) SRAM cells at low supply voltage in sub-0.4V regime
2015 · Hao Qiu, Tomoko Mizutani, et al. · Symposium on VLSI Technology · 12
Ultralow-voltage design and technology of silicon-on-thin-buried-oxide (SOTB) CMOS for highly energy efficient electronics in IoT era
2014 · Shiro Kamohara, Nobuyuki Sugii, et al. · Symposium on VLSI Technology · 12
Ultralow-Power SOTB CMOS Technology Operating Down to 0.4 V
2014 · Nobuyuki Sugii, Yoshiki Yamamoto, et al. · Journal of Low Power Electronics and Applications · 12
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A Robust SOI SRAM Architecture by using Advanced ABC technology for 32nm node and beyond LSTP devices
2007 · Yuuichi Hirano, Mikio Tsujiuchi, et al. · Symposium on VLSI Technology · 10
A Novel Low Leakage-Current Ni SALICIDE Process in nMOSFETs on Si(110) Substrate
2007 · T. Yamaguchi, K. Kashihara, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 10
Cost-Effective 28-nm LSTP CMOS using gate-first metal gate/high-k technology
2006 · T. Tomimatsu, Y. Goto, et al. · Symposium on VLSI Technology · 10
Comparison and distribution of minimum operation voltage in fully depleted silicon-on-thin-buried-oxide and bulk static random access memory cells
2014 · Tomoko Mizutani, Yoshiki Yamamoto, et al. · Japanese Journal of Applied Physics · 9
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Suppression of die-to-die delay variability of silicon on thin buried oxide (SOTB) CMOS circuits by balanced P/N drivability control with back-bias for ultralow-voltage (0.4 V) operation
2013 · H. Makiyama, Y. Yamamoto, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 8
Novel single p+poly-Si/Hf/SiON gate stack technology on silicon-on-thin-buried-oxide (SOTB) for ultra-low leakage applications
2015 · Y. Yamamoto, H. Makiyama, et al. · Symposium on VLSI Technology · 7
Works count: 106
Citation count: 716
H-index: 15
I10-index: 22
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