Get started
Author

Paolo Mantovani

Observed name: Mantovani, Paolo
Institution: Columbia University
ORCID: 0000-0002-1901-8732
Observed ORCID: 0000-0002-1901-8732
OpenAlex ID: A5086890914
Agile SoC development with open ESP
2020 · Paolo Mantovani, Davide Giri, et al. · 135
PDF
An Analysis of Accelerator Coupling in Heterogeneous Architectures
2015 · Emilio G. Cota, Paolo Mantovani, et al. · ACM/IEEE Design Automation Conference (DAC) · 105
A Switched-Inductor Integrated Voltage Regulator With Nonlinear Feedback and Network-on-Chip Load in 45 nm SOI
2012 · Noah Sturcken, Michele Petracca, et al. · IEEE Journal of Solid-State Circuits · 59
A wireless subdural-contained brain–computer interface with 65,536 electrodes and 1,024 channels
2025 · Taesung Jung, Nanyu Zeng, et al. · Nature Electronics · 40
An FPGA-based infrastructure for fine-grained DVFS analysis in high-performance embedded systems
2016 · Paolo Mantovani, Emilio G. Cota, et al. · ACM/IEEE Design Automation Conference (DAC) · 40
PDF
Accelerators and Coherence: An SoC Perspective
2018 · Davide Giri, Paolo Mantovani, et al. · IEEE Micro · 39
System-Level Optimization of Accelerator Local Memory for Heterogeneous Systems-on-Chip
2016 · Christian Pilato, Paolo Mantovani, et al. · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · 36
PDF
Accelerator Integration for Open-Source SoC Design
2021 · Davide Giri, Kuan-Lin Chiu, et al. · IEEE Micro · 30
HL5: A 32-bit RISC-V Processor Designed with High-Level Synthesis
2020 · Paolo Mantovani, Robert Margelli, et al. · Custom Integrated Circuits Conference · 30
Handling large data sets for high-performance embedded applications in heterogeneous systems-on-chip
2016 · Paolo Mantovani, Emilio G. Cota, et al. · International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES) · 29
PDF
A 12nm Agile-Designed SoC for Swarm-Based Perception with Heterogeneous IP Blocks, a Reconfigurable Memory Hierarchy, and an 800MHz Multi-Plane NoC
2022 · Tianyu Jia, Paolo Mantovani, et al. · European Solid-State Circuits Conference (ESSCIRC) · 26
14.5 A 12nm Linux-SMP-Capable RISC-V SoC with 14 Accelerator Types, Distributed Hardware Power Management and Flexible NoC-Based Data Orchestration
2024 · Maico Cassel Dos Santos, Tianyu Jia, et al. · Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference · 25
High-level synthesis of accelerators in embedded scalable platforms
2016 · Paolo Mantovani, Giuseppe Di Guglielmo, et al. · Asia and South Pacific Design Automation Conference (ASP-DAC) · 24
NoC-Based Support of Heterogeneous Cache-Coherence Models for Accelerators
2018 · Davide Giri, Paolo Mantovani, et al. · IEEE/ACM International Symposium on Networks-on-Chip (NOCS) · 23
Accelerator Memory Reuse in the Dark Silicon Era
2012 · Emilio G. Cota, Paolo Mantovani, et al. · IEEE Computer Architecture Letters · 21
PDF
Broadening the exploration of the accelerator design space in embedded scalable platforms
2017 · Luca Piccolboni, Paolo Mantovani, et al. · IEEE High Performance Extreme Computing Conference · 18
Enabling Heterogeneous, Multicore SoC Research with RISC-V and ESP
2022 · Zuckerman, Joseph, Mantovani, Paolo, et al. · arXiv (Cornell University) · 16
PDF
System-level memory optimization for high-level synthesis of component-based SoCs
2014 · Christian Pilato, Paolo Mantovani, et al. · International Conference on Hardware/Software Codesign and System Synthesis · 15
PDF
NoC-Based support of heterogeneous cache-coherence models for accelerators
2018 · Davide Giri, Paolo Mantovani, et al. · Networks-on-Chips · 14
Towards a Complete Methodology for Synthesizing Bundled-Data Asynchronous Circuits on FPGAs
2019 · Kshitij Bhardwaj, Paolo Mantovani, et al. · International Symposium on Low Power Electronics and Design (ISLPED) · 11
Teaching Heterogeneous Computing with System-Level Design Methods
2019 · Luca P. Carloni, Emilio G. Cota, et al. · Workshop on Computer Architecture Education (WCAE) · 9
PDF
System-Level Design of Networks-on-Chip for Heterogeneous Systems-on-Chip
2017 · Young Jin Yoon, Paolo Mantovani, et al. · IEEE/ACM International Symposium on Networks-on-Chip (NOCS) · 9
PDF
On the design of scalable and reusable accelerators for big data applications
2016 · Christian Pilato, Qirui Xu, et al. · ACM International Conference on Computing Frontiers (CF) · 9
PDF
A Scalable Methodology for Agile Chip Development with Open-Source Hardware Components
2022 · Maico Cassel dos Santos, Tianyu Jia, et al. · International Conference on Computer Aided Design · 8
Exploiting Private Local Memories to Reduce the Opportunity Cost of Accelerator Integration
2016 · Emilio G. Cota, Paolo Mantovani, et al. · International Conference on Supercomputing · 7
Works count: 38
Citation count: 800
H-index: 16
I10-index: 20
Year
Topic
Type