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Author

Jiaoyan Chen

ORCID: 0000-0002-0287-951X
Observed ORCID: 0000-0002-0287-951X
OpenAlex ID: A5101985191
Linear Compositional Delay Model for the Timing Analysis of Sub-Powered Combinational Circuits
2014 · Jiaoyan Chen, Christian Spagnol, et al. · IEEE Computer Society Annual Symposium on VLSI · 12
Probabilistic Gate Level Fault Modeling for Near and Sub-Threshold CMOS Circuits
2014 · Alexandru Amaricai, Sergiu Nimara, et al. · Euromicro Conference on Digital System Design (DSD) · 11
Design and analysis of a novel 8T SRAM cell for adiabatic and non-adiabatic operations
2010 · Jiaoyan Chen, Dilip Vasudevan, et al. · IEEE International Conference on Electronics, Circuits and Systems (ICECS) · 9
Inverse Gaussian distribution based timing analysis of Sub-threshold CMOS circuits
2015 · Jiaoyan Chen, Sorin Cotofana, et al. · Microelectronics Reliability · 8
Ultra Low Power Booth Multiplier Using Asynchronous Logic
2012 · Jiaoyan Chen, Emanuel Popovici, et al. · IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC) · 5
Robust sub-powered asynchronous logic
2014 · Jiaoyan Chen, Arnaud Tisserand, et al. · International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS) · 3
Ultra Low Power Asynchronous Charge Sharing Logic
2012 · Jiaoyan Chen, Dilip Vasudevan, et al. · Journal of Low Power Electronics · 2
Asynchronous Charge Sharing Power Consistent Montgomery Multiplier
2015 · Jiaoyan Chen, Arnaud Tisserand, et al. · IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC) · 1
Reliability aware logic synthesis through rewriting
2014 · Satish Grandhi, Christian Spagnol, et al. · IEEE International System-on-Chip Conference (SOCC) · 1
Works count: 9
Citation count: 52
H-index: 5
I10-index: 2
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