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Author

T. Ogawara

Observed institutions: NEC (Japan), Toshiba (Japan)
OpenAlex ID: A5110134890
Single-chip 4-channel 155 Mb/s CMOS LSI chip for ATM SONET/SDH framing and clock/data recovery
2002 · T. Nakao, M. Kuwahara, et al. · Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference · 4
A 10-bit 60 MHz EPROM trimming DAC
1991 · T. Ogawara, T. Takiguchi · International Conference on Consumer Electronics · 1
B-5-164 RFID anti-collision performance in random error communication link
2005 · Yuusuke Kawakita, Jin Mitsugi, et al. · Proceedings of the Society Conference of IEICE
The Phase Locked Loop for Clock Recovery Used in a Single-Chip 4-Channel 155Mb/s CMOS ATM Physical Layer Controller LSI(Special Issue on Multimedia, Network, and DRAM LSIs)
1998 · Takehiko Nakao, M. Kuwahara, et al. · IEICE Transactions on Electronics
Chip for ATM SONETlSDH Framing and ClocWData Recovery
1997 · Takehiko Nakao, M. Kuwahara, et al.
Works count: 5
Citation count: 5
H-index: 1
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