Author

Barry Daly

Observed name: B. Daly

Observed institution: Rambus (United States)

OpenAlex ID: A5110142183

A 40 Gb/s Serial Link Transceiver in 28 nm CMOS Technology

2014 · Reza Navid, E-Hung Chen, et al. · IEEE Journal of Solid-State Circuits · 89

A 7.5Gb/s 10-Tap DFE Receiver with First Tap Partial Response, Spectrally Gated Adaptation, and 2nd-Order Data-Filtered CDR

2007 · Brian S. Leibowitz, Jade Kizer, et al. · Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference · 54

A 32mW 7.4Gb/s protocol-agile source-series-terminated transmitter in 45nm CMOS SOI

2010 · Wayne D Dettloff, John C Eble, et al. · Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference · 47

A 6.4-Gb/s Near-Ground Single-Ended Transceiver for Dual-Rank DIMM Memory Interface Systems

2013 · Michael Bucher, Ravi T. Kollipara, et al. · IEEE Journal of Solid-State Circuits · 35

A Fast-Lock, Jitter Filtering All-Digital DLL Based Burst-Mode Memory Interface

2014 · Masum Hossain, Farrukh Aquil, et al. · IEEE Journal of Solid-State Circuits · 24

A 5.6Gb/s 2.4mW/Gb/s bidirectional link with 8ns power-on

2011 · Jared Zerbe, Barry Daly, et al. · Symposium on VLSI Circuits · 21

A 5 Gb/s Link With Matched Source Synchronous and Common-Mode Clocking Techniques

2011 · Jared Zerbe, Barry Daly, et al. · IEEE Journal of Solid-State Circuits · 18

A 40-Gb/s serial link transceiver in 28-nm CMOS technology

2014 · E-Hung Chen, Masum Hossain, et al. · Symposium on VLSI Circuits · 12

A 4×40 Gb/s quad-lane CDR with shared frequency tracking and data dependent jitter filtering

2014 · Masum Hossain, E-Hung Chen, et al. · Symposium on VLSI Circuits · 10

A 1-4 Gbps quad transceiver cell using PLL with gate-current leakage compensator in 90nm CMOS

2004 · Y. Frans, N. Nguyen, et al. · Symposium on VLSI Circuits · 9

A 2.3–4GHz injection-locked clock multiplier with 55.7% lock range and 10-ns power-on

2012 · Dustin Dunwell, Anthony Chan Carusone, et al. · Custom Integrated Circuits Conference · 8

A 400MHz – 1.6GHz fast lock, jitter filtering ADDLL based burst mode memory interface

2013 · Masum Hossain, Farrukh Aquil, et al. · Symposium on VLSI Circuits · 4

A 6.4/3.2/1.6 Gb/s low power interface with all digital clock multiplier for on-the-fly rate switching

2012 · Masum Hossain, Kambiz Kaviani, et al. · Custom Integrated Circuits Conference · 4

A 5Gb/s link with clock edge matching and embedded common mode clock for low power interfaces

2010 · Jared Zerbe, Barry Daly, et al. · Symposium on VLSI Circuits · 1

Works count: 14

Citation count: 336

H-index: 9

I10-index: 9