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J. Pille

Observed name: Jurgen Pille
Institution: IBM (Germany)
OpenAlex ID: A5110149229
Overview of the Architecture, Circuit Design, and Physical Implementation of a First-Generation Cell Processor
2005 · D.C. Pham, T. Aipperspach, et al. · IEEE Journal of Solid-State Circuits · 233
Implementation of the CELL Broadband Engine in a 65nm SOI Technology Featuring Dual-Supply SRAM Arrays Supporting 6GHz at 1.3V
2007 · J. Pille, C. Adams, et al. · Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference · 48
Migration of Cell Broadband Engine from 65nm SOI to 45nm SOI
2008 · O. Takahashi, C. Adams, et al. · Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference · 19
IBM POWER8 circuit design and energy optimization
2015 · V. Zyuban, J. Friedrich, et al. · IBM Journal of Research and Development · 17
Circuit Design Techniques for a First-Generation Cell Broadband Engine Processor
2006 · J. Warnock, D. Wendel, et al. · IEEE Journal of Solid-State Circuits · 16
The circuits and physical design of the synergistic processor element of a CELL processor
2005 · O. Takahashi, R. Cook, et al. · Symposium on VLSI Circuits · 16
A 1.8-GHz instruction window buffer for an out-of-order microprocessor core
2001 · J. Leenstra, J. Pille, et al. · IEEE Journal of Solid-State Circuits · 12
A 4GHz, low latency TCAM in 14nm SOI FinFET technology using a high performance current sense amplifier for AC current surge reduction
2015 · Alexander Fritsch, Michael Kugel, et al. · European Solid-State Circuits Conference (ESSCIRC) · 10
Microarchitecture and implementation of the synergistic processor in 65-nm and 90-nm SOI
2007 · B. Flachs, S. Asano, et al. · IBM Journal of Research and Development · 9
The circuit design of the synergistic processor element of a CELL processor
2005 · O. Takahashi, R. Cook, et al. · International Conference on Computer Aided Design · 9
A 1.8 GHz Instruction Window Buffer
2002 · J. Leenstra, J. Pille, et al. · Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference · 8
IBM POWER7 processor circuit design
2011 · D. F. Wendel, J. Barth, et al. · IBM Journal of Research and Development · 6
The vector fixed point unit of the synergistic processor element of the cell architecture processor
2005 · N. Mading, J. Leenstra, et al. · European Solid-State Circuits Conference (ESSCIRC) · 6
The Vector Fixed Point Unit of the Synergistic Processor Element of the Cell Architecture Processor
2006 · N. Mading, J. Leenstra, et al. · Design, Automation, and Test in Europe · 5
A system of array families and synthesized soft arrays for the POWER9™ processor in 14nm SOI FinFET technology
2017 · P. Salz, A. Frisch, et al. · European Solid-State Circuits Conference (ESSCIRC) · 3
Implementation of the 65nm Cell Broadband Engine
2007 · M. Riley, B. Flachs, et al. · Custom Integrated Circuits Conference · 3
A 32nm 0.5V-supply dual-read 6T SRAM
2010 · J.B. Kuang, J.D. Schaub, et al. · Custom Integrated Circuits Conference · 2
The Design and Implementation of a Low-Overhead Supply-Gated SRAM
2006 · J.b. Kuang, H.c. Ngo, et al. · European Solid-State Circuits Conference (ESSCIRC) · 2
Works count: 18
Citation count: 424
H-index: 9
I10-index: 8
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