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Author

Anying Jiang

Institution: Nanjing University
Observed institution: Nanjing University
ORCID: 0009-0005-9804-8073
Observed ORCID: 0009-0005-9804-8073
OpenAlex ID: A5111290194
An 11T1C Bit-Level-Sparsity-Aware Computing- in-Memory Macro With Adaptive Conversion Time and Computation Voltage
2024 · Ye Lin, Yuandong Li, et al. · IEEE Transactions on Circuits and Systems I Regular Papers · 8
A 65nm 100MS/s-400MS/s Multi-Column SAR/SS ADC with Reconfigurable 2-8 Bit Resolution for Optical and In-memory Computing
2025 · Anying Jiang, Ye Lin, et al. · IEEE International Symposium on Circuits and Systems proceedings · 1
A 250 Mbps 6.5375 Mb/s/µm2 PVT-robust TRNG with charge-trap programming (CTP)-based dynamic 0/1 bias cancellation
2026 · Ye Lin, Junjie Shen, et al. · Science China Information Sciences
CD-PIM: A High-Bandwidth and Compute-Efficient LPDDR5-Based PIM for Low-Batch LLM Acceleration on Edge-Device
2026 · Ye Lin, Chao Fang, et al.
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In-Situ Storing NVSRAM Macro With In-Bitline Copy and Full-Array Boolean Logic Operation Based on Charge-Trap Programming (CTP) Method
2026 · Ye Lin, Anying Jiang, et al. · IEEE Transactions on Circuits and Systems I Regular Papers
Investigation of Post-Programming Characteristics for Charge-Trap Transistors in Standard 28nm CMOS
2026 · Ye Lin, Jun Ma, et al. · IEEE Electron Devices Technology & Manufacturing Conference (EDTM)
A Novel Bit-Adjustable Column-Parallel ADC for Scalable Emerging Computing Systems
2025 · Anying Jiang, Ye Lin, et al. · IEEE Transactions on Circuits & Systems II Express Briefs
An Offset-Cancellation Technique Using Charge-Trap Transistors and Asynchronous Programming Scheme
2024 · Ye Lin, Anying Jiang, et al. · IEEE Transactions on Circuits & Systems II Express Briefs
Works count: 8
Citation count: 9
H-index: 1
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