Author

Y. Hayami

Observed institutions: Fujitsu (Japan), Nissan (Japan)

OpenAlex ID: A5111426447

Technology booster using strain-enhancing laminated SiN (SELS) for 65nm node HP MPUs

2005 · K. Goto, S. Satoh, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 31

High performance 30 nm gate bulk CMOS for 45 nm node with σ-shaped SiGe-SD

2006 · H. Ohta, Y. Kim, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 27

High-Performance and Low-Power Bulk Logic Platform Utilizing FET Specific Multiple-Stressors with Highly Enhanced Strain and Full-Porous Low-k Interconnects for 45-nm CMOS Technology

2007 · T. Miyashita, K. Ikeda, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 22

High-Performance Low Operation Power Transistor for 45nm Node Universal Applications

2006 · T. Sugii, K. Hashimoto, et al. · Symposium on VLSI Technology · 11

Physical and electrical analysis of the stress memorization technique (SMT) using poly-gates and its optimization for beyond 45-nm high-performance applications

2008 · T. Miyashita, T. Owada, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 10

Integration Strategy of Embedded SiGe S/D CMOS from Viewpoint of Performance and Cost for 45nm-Node and Beyond

2008 · K. Ikeda, T. Miyashita, et al. · IEEE International Power Modulator Symposium and High-Voltage Workshop (IPMHVC) · 5

45-nm node CMOS integration with a novel STI structure and full-NCS/Cu interlayers for low-operation-power (lop) applications

2006 · M. Okuno, K. Okabe, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 5

Advanced junction profile design scheme by low-temperature millisecond annealing and co-implant for high performance CMOS

2008 · K. Ikeda, T. Miyashita, et al. · Symposium on VLSI Technology · 4

Suppression of Defect Formation and Their Impact on Short Channel Effects and Drivability of pMOSFET with SiGe Source/Drain

2006 · Y. S. Kim, Y. Shimamune, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 3

Low on-resistance LDMOSFETs with DSS (a drain window surrounded by source windows) pattern layout

2002 · M. Hoshi, Y. Shimoida, et al. · IEEE International Symposium on Power Semiconductor Devices and ICs/Proceedings of the International Symposium on Power Semiconductor Devices & ICs/Proceedings of the ... International Symposium on Power Semiconductor Devices & ICs/Proceedings of the ... International Symposium on Power Semiconductor Devices and ICs · 3

Low on-resistance lateral U-gate MOSFET with DSS pattern layout

2003 · Y. Shimoida, Y. Hayami, et al. · IEEE International Symposium on Power Semiconductor Devices and ICs/Proceedings of the International Symposium on Power Semiconductor Devices & ICs/Proceedings of the ... International Symposium on Power Semiconductor Devices & ICs/Proceedings of the ... International Symposium on Power Semiconductor Devices and ICs · 2

Novel Stack-SIN Gate Dielectrics for High Performance 30 nm CMOS for 45 nm Node with Uniaxial Strained Silicon

2006 · H. Ohta, M. Hori, et al. · Symposium on VLSI Technology · 1

A highly robust SiGe source drain technology realized by disposable sidewall spacer (DSW) for 65nm node and beyond

2005 · Y.S. Kim, T. Mori, et al. · European Solid-State Device Research Conference · 1

wilth H'ighly Enhanced Strailn andFull-Porous Low-kInterconnects for45-nmCMOS Technology

2007 · Tomofumi Miyashita, Y. Sambonsugi, et al.

Works count: 14

Citation count: 125

H-index: 5

I10-index: 5