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Masashi Yamaoka

OpenAlex ID: A5111663037
13.5 A 512Gb 3-bit/Cell 3D Flash Memory on 128-Wordline-Layer with 132MB/s Write Performance Featuring Circuit-Under-Array Technology
2019 · Chang Siau, Kwang-Ho Kim, et al. · Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference · 85
7.1 A low-power 64Gb MLC NAND-flash memory in 15nm CMOS technology
2015 · Mario Sako, Yoshihisa Watanabe, et al. · Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference · 34
A Low Power 64 Gb MLC NAND-Flash Memory in 15 nm CMOS Technology
2015 · Mario Sako, Yoshihisa Watanabe, et al. · IEEE Journal of Solid-State Circuits · 27
13.5 A 128Gb 1b/Cell 96-Word-Line-Layer 3D Flash Memory to Improve Random Read Latency with t PROG =75µs and t R =4µs
2020 · Toshiyuki Kouchi, Noriyasu Kumazaki, et al. · Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference · 18
15nm CMOS技術による低電力64Gb MLC NANDフラッシュメモリ
2015 · Mario Sako, Yoshihisa Watanabe, et al. · IEICE Technical Report; IEICE Tech. Rep.
Works count: 5
Citation count: 164
H-index: 4
I10-index: 4
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