Author

Navin Srivastava

Observed name: N. Srivastava

Observed institutions: University of California, Santa Barbara, Mentor Graphics (United States)

OpenAlex ID: A5111919138

Carbon Nanomaterials for Next-Generation Interconnects and Passives: Physics, Status, and Prospects

2009 · Hong Li, Chuan Xu, et al. · IEEE Transactions on Electron Devices · 443

A thermally-aware performance analysis of vertically integrated (3-D) processor-memory hierarchy

2006 · G.L. Loi, B. Agrawal, et al. · ACM/IEEE Design Automation Conference (DAC) · 206

Are carbon nanotubes the future of VLSI interconnections?

2006 · K. Banerjee, N. Srivastava · ACM/IEEE Design Automation Conference (DAC) · 131

Interconnect challenges for nanoscale electronic circuits

2004 · Navin Srivastava, Kaustav Banerjee · JOM · 72

A Comparative Scaling Analysis of Metallic and Carbon Nanotube Interconnections for Nanometer Scale VLSI Technologies

2004 · Navin Srivastava, Kaustav Banerjee · 63

Current Status and Future Perspectives of Carbon Nanotube Interconnects

2008 · Kaustav Banerjee, Hong Li, et al. · IEEE Conference on Nanotechnology (IEEE NANO) · 59

Introspective 3D chips

2006 · Shashidhar Mysore, Banit Agrawal, et al. · International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS) · 52

Carbon Nanotube Vias: Does Ballistic Electron–Phonon Transport Imply Improved Performance and Reliability?

2011 · Hong Li, Navin Srivastava, et al. · IEEE Transactions on Electron Devices · 35

Electrothermal engineering in the nanometer era

2006 · Kaustav Banerjee, Sheng-Chih Lin, et al. · Asia and South Pacific Design Automation Conference (ASP-DAC) · 24

Interconnect Modeling and Analysis in the Nanometer Era: Cu and Beyond

2005 · Kaustav Banerjee, Sungjun Im, et al. · 20

Carbon Nanotube Vias: A Reality Check

2007 · Hong Li, Navin Srivastava, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 17

Can Carbon Nanotubes Extend the Lifetime of On-Chip Electrical Interconnections?

2006 · Kaustav Banerjee, Sungjun Im, et al. · International Conference on Nano-Networks (Nano-Net) · 8

Introspective 3D chips

2006 · Shashidhar Mysore, Banit Agrawal, et al. · ACM SIGOPS Operating Systems Review · 6

3D Integration for Introspection

2007 · Shashidhar Mysore, Banit Agrawal, et al. · IEEE Micro · 4

Efficient 3D high-frequency impedance extraction for general interconnects and inductors above a layered substrate

2010 · Navin Srivastava, Roberto Suaya, et al. · Design, Automation, and Test in Europe · 3

High-Frequency Mutual Impedance Extraction of VLSI Interconnects In the Presence of a Multi-layer Conducting Substrate

2008 · Navin Srivastava, Roberto Suaya, et al. · Design, Automation, and Test in Europe · 3

Modeling and Extraction of Nanometer Scale Interconnects: Challenges and Opportunities (Invited)

2006 · Roberto Suaya, Rafael Escovar, et al. · 3

Corrections to “Analytical Expressions for High-Frequency VLSI Interconnect Impedance Extraction in the Presence of a Multilayer Conductive Substrate” [Jul 09 1047-1060

2010 · Navin Srivastava, Chuan Xu, et al. · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · 2

Introspective 3D chips

2006 · Shashidhar Mysore, Banit Agrawal, et al. · ACM SIGARCH Computer Architecture News · 2

An efficient 3D Green's function approach for fast impedance extraction of interconnects and spiral inductors in CMOS RF/Millimeter-wavelength circuits

2010 · Navin Srivastava, Roberto Suaya, et al. · IEEE International Interconnect Technology Conference (IITC)

Introspective 3D chips

2006 · Shashidhar Mysore, Banit Agrawal, et al. · ACM SIGPLAN Notices

Works count: 26

Citation count: 1,153

H-index: 11

I10-index: 11