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Tadahiko Sugibayashi

Nonvolatile Magnetic Flip-Flop for Standby-Power-Free SoCs
2009 · Noboru Sakimura, Tadahiko Sugibayashi, et al. · IEEE Journal of Solid-State Circuits · 175
10.5 A 90nm 20MHz fully nonvolatile microcontroller for standby-power-critical applications
2014 · Noboru Sakimura, Yukihide Tsuji, et al. · Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference · 111
Low Current Perpendicular Domain Wall Motion Cell for Scalable High-Speed MRAM
2006 · Shunsuke Fukami, Tetsuya Suzuki, et al. · Symposium on VLSI Technology · 105
Nonvolatile logic-in-memory array processor in 90nm MTJ/MOS achieving 75% leakage reduction using cycle-based power gating
2013 · M. Natsui, D. Suzuki, et al. · Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference · 70
Nonvolatile Logic-in-Memory LSI Using Cycle-Based Power Gating and its Application to Motion-Vector Prediction
2014 · Masanori Natsui, Daisuke Suzuki, et al. · IEEE Journal of Solid-State Circuits · 63
High-speed simulator including accurate MTJ models for spintronics integrated circuit design
2012 · Noboru Sakimura, Ryusuke Nebashi, et al. · IEEE International Symposium on Circuits and Systems proceedings · 60
Nonvolatile Magnetic Flip-Flop for standby-power-free SoCs
2008 · Noboru Sakimura, Tadahiko Sugibayashi, et al. · Custom Integrated Circuits Conference · 59
MRAM Cell Technology for Over 500-MHz SoC
2007 · Noboru Sakimura, Tadahiko Sugibayashi, et al. · IEEE Journal of Solid-State Circuits · 54
20-nm magnetic domain wall motion memory with ultralow-power operation
2013 · S. Fukami, M. Yamanouchi, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 53
Etching Magnetic Tunnel Junction with Metal Etchers
2010 · Keizo Kinoshita, Hiroaki Utsumi, et al. · Japanese Journal of Applied Physics · 51
Programmable cell array using rewritable solid-electrolyte switch integrated in 90nm CMOS
2011 · Makoto Miyamura, Shogo Nakaya, et al. · Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference · 45
A Nonvolatile Associative Memory-Based Context-Driven Search Engine Using 90 nm CMOS/MTJ-Hybrid Logic-in-Memory Architecture
2014 · Hooman Jarollahi, Naoya Onizawa, et al. · IEEE Journal on Emerging and Selected Topics in Circuits and Systems · 42
A 30-ns 256-Mb DRAM with a multidivided array structure
1993 · T. Sugibayashi, T. Takeshima, et al. · IEEE Journal of Solid-State Circuits · 40
A 90nm 12ns 32Mb 2T1MTJ MRAM
2009 · R. Nebashi, N. Sakimura, et al. · Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference · 37
Fabrication of a 99%-Energy-Less Nonvolatile Multi-Functional CAM Chip Using Hierarchical Power Gating for a Massively-Parallel Full-Text-Search Engine
2013 · Satoru Matsunaga, Noboru Sakimura, et al. · Symposium on VLSI Circuits · 31
A content addressable memory using magnetic domain wall motion cells
2011 · Ryusuke Nebashi, Noboru Sakimura, et al. · Symposium on VLSI Circuits · 31
High-speed and reliable domain wall motion device: Material design for embedded memory and logic application
2012 · S. Fukami, M. Yamanouchi, et al. · Symposium on VLSI Technology · 30
Improvement of Thermal Stability of Magnetoresistive Random Access Memory Device with SiN Protective Film Deposited by High-Density Plasma Chemical Vapor Deposition
2008 · Katsumi Suemitsu, Yuichi Kawano, et al. · Japanese Journal of Applied Physics · 28
PDF
A 512kb cross-point cell MRAM
2003 · N. Sakimura, T. Sugibayashi, et al. · Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference · 27
A 1-Gb DRAM for file applications
1995 · T. Sugibayashi, I. Naritake, et al. · IEEE Journal of Solid-State Circuits · 26
A power-gated MPU with 3-microsecond entry/exit delay using MTJ-based nonvolatile flip-flop
2013 · H. Koike, T. Ohsawa, et al. · IEEE Asian Solid-State Circuits Conference (A-SSCC) · 24
A 1 Gb DRAM for file applications
2002 · T. Sugibayashi, I. Naritake, et al. · Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference · 23
A 16Mb MRAM with FORK Wiring Scheme and Burst Modes
2006 · Y. Iwata, K. Tsuchida, et al. · Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference · 20
A 16-Mb Toggle MRAM With Burst Modes
2007 · Tadahiko Sugibayashi, Noboru Sakimura, et al. · IEEE Journal of Solid-State Circuits · 19
A 30 ns 256 Mb DRAM with multi-divided array structure
1993 · T. Sugibayashi, T. Takeshima, et al. · Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference · 18
Works count: 121
Citation count: 1,582
H-index: 22
I10-index: 36
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