Author

Behrooz Parhami

Observed name: B. Parhami

Institutions: University of California, Santa Barbara, University of California, Los Angeles

Observed institutions: University of Waterloo, University of California, Santa Barbara, University of California, Los Angeles, University of California System, Carleton University

OpenAlex ID: A5111931820

Computer Arithmetic: Algorithms and Hardware Designs

1999 · Behrooz Parhami · 1,146

Introduction to Parallel Processing: Algorithms and Architectures

1999 · Behrooz Parhami · Thammasat University Digital Collections · 324

Fault-Tolerant Reversible Circuits

2006 · Behrooz Parhami · Asilomar Conference on Signals, Systems and Computers (ACSSC) · 246

Generalized signed-digit number systems: a unifying framework for redundant number representations

1990 · B. Parhami · IEEE Transactions on Computers · 183

Carry-free addition of recoded binary signed-digit numbers

1988 · B. Parhami · IEEE Transactions on Computers · 91

Associative memories and processors: An overview and selected bibliography

1973 · B. Parhami · Proceedings of the IEEE · 80

Efficient Hamming Weight Comparators for Binary Vectors Based on Accumulative and Up/Down Parallel Counters

2009 · B. Parhami · IEEE Transactions on Circuits & Systems II Express Briefs · 65

Accumulative parallel counters

2002 · B. Parhami, Chi-Hsiang Yeh · Asilomar Conference on Signals, Systems and Computers (ACSSC) · 50

An approximate sign detection method for residue numbers and its application to RNS division

1994 · C.Y. Hung, B. Parhami · Computers & Mathematics with Applications · 47

PDF

Weighted two-valued digit-set encodings: unifying efficient hardware representation schemes for redundant number systems

2005 · G. Jaberipur, B. Parhami, et al. · IEEE Transactions on Circuits and Systems I Fundamental Theory and Applications · 40

On the implementation of arithmetic support functions for generalized signed-digit number systems

1993 · B. Parhami · IEEE Transactions on Computers · 36

Unified Approach to the Design of Modulo-(2^n +/- 1) Adders Based on Signed-LSB Representation of Residues

2009 · Ghassem Jaberipur, Behrooz Parhami · IEEE Symposium on Computer Arithmetic (ARITH) · 34

Biswapped Networks and Their Topological Properties

2007 · Wenjun Xiao, Weidong Chen, et al. · ACIS International Conference on Software Engineering, Artificial Intelligence, Networking and Parallel/Distributed Computing (SNPD) · 33

Majority-Logic, its applications, and atomic-scale embodiments

2020 · Behrooz Parhami, Dariush Abedi, et al. · Computers & Electrical Engineering · 28

PDF

Computing with logarithmic number system arithmetic: Implementation methods and performance benefits

2020 · Behrooz Parhami · Computers & Electrical Engineering · 27

Arithmetic with binary-encoded balanced ternary numbers

2013 · Behrooz Parhami, Michael McKeown · Asilomar Conference on Signals, Systems and Computers (ACSSC) · 25

Data-driven control scheme for linear arrays: application to a stable insertion sorter

1999 · B. Parhami, Ding-Ming Kwai · IEEE Transactions on Parallel and Distributed Systems · 24

Optimal table lookup schemes for VLSI implementation of input/output conversions and other residue number operations

2002 · B. Parhami, C.Y. Hung · SiPS ... design and implementation - IEEE Workshop on Signal Processing Systems · 23

Adapting Computer Arithmetic Structures to Sustainable Supercomputing in Low-Power, Majority-Logic Nanotechnologies

2018 · Ghassem Jaberipur, Behrooz Parhami, et al. · IEEE Transactions on Sustainable Computing · 21

Constant-time addition with hybrid-redundant numbers: Theory and implementations

2007 · Ghassem Jaberipur, Behrooz Parhami · Integration · 21

Efficient realisation of arithmetic algorithms with weighted collection of posibits and negabits

2012 · G. Jaberipur, B. Parhami · IET Computers & Digital Techniques · 20

Logarithmic arithmetic as an alternative to floating-point: A review

2013 · Manik Chugh, Behrooz Parhami · Asilomar Conference on Signals, Systems and Computers (ACSSC) · 19

Stored-transfer representations with weighted digit-set encodings for ultrahigh-speed arithmetic

2007 · G. Jaberipur, B. Parhami · IET Circuits Devices & Systems · 16

An Efficient Universal Addition Scheme for All Hybrid-Redundant Representations with Weighted Bit-Set Encoding

2006 · Ghassem Jaberipur, Behrooz Parhami, et al. · The Journal of VLSI Signal Processing Systems for Signal Image and Video Technology · 16

Weighted bit-set encodings for redundant digit sets: theory and applications

2003 · G. Jaberipur, B. Parhami, et al. · Asilomar Conference on Signals, Systems and Computers (ACSSC) · 13

Works count: 98

Citation count: 2,939

H-index: 20

I10-index: 34