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R. Yung
Institution:
University of California, Berkeley
Observed institutions:
Intel (United States),
University of California, Berkeley
OpenAlex ID:
A5113615098
Caching processor general registers
2002
·
R. Yung
, N.C. Wilhelm
·
IEEE International Conference on Computer Design: VLSI in Computers and Processors (ICCD)
·
55
UltraSPARC: the next generation superscalar 64-bit SPARC
2002
·
D. Greenley
, J. Bauman
, et al.
·
IEEE Computer Society International Conference (COMPCON Spring)
·
50
Multiple-Level Logic Optimization System
2003
·
R. Brayton
, E. Detjens
, et al.
·
Springer eBooks
·
36
Future trend of microprocessor design
2002
·
R. Yung
, Stefan Rusu
, et al.
·
12
Design decisions influencing the UltraSPARC's instruction fetch architecture
2002
·
R. Yung
·
IEEE/ACM International Symposium on Microarchitecture (MICRO)
·
4
Extending a Prolog architecture for high performance numeric computations
2003
·
R. Yung
, A.M. Despain
, et al.
·
Hawaii International Conference on System Sciences (HICSS)
Microprocessor technologies for the 21st century
1999
·
R. Yung
·
Asia and South Pacific Design Automation Conference (ASP-DAC)
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Works count:
7
Citation count:
157
H-index:
4
I10-index:
4
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