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Sylvain Engels

Ultra-wide body-bias range LDPC decoder in 28nm UTBB FDSOI technology
2013 · Philippe Flatresse, Bastien Giraud, et al. · Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference · 79
A predictive bottom-up hierarchical approach to digital system reliability
2012 · V. Huard, E. Pion, et al. · IEEE International Reliability Physics Symposium proceedings · 32
Logical effort model extension to propagation delay representation
2006 · B. Lasbouygues, S. Engels, et al. · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · 30
A Fine-Grain Variation-Aware Dynamic ${\rm Vdd}$ -Hopping AVFS Architecture on a 32 nm GALS MPSoC
2014 · Ivan Miro-Panades, Edith Beigne, et al. · IEEE Journal of Solid-State Circuits · 25
Ultra-Wide Voltage Range Designs in Fully-Depleted Silicon-On-Insulator FETs
2013 · E. Beigne, A. Valentian, et al. · Design, Automation, and Test in Europe · 19
Comparison of 65nm LP bulk and LP PD-SOI with adaptive power gate body bias for an LDPC codec
2011 · Julien Le Coz, Philippe Flatresse, et al. · Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference · 13
A Simple Statistical Timing Analysis Flow and Its Application to Timing Margin Evaluation
2007 · V. Migairou, R. Wilson, et al. · Lecture notes in computer science · 9
A low–power 16–channel AD converter and digital processor ASIC
2002 · Daniel Subiela, Sylvain Engels, et al. · European Solid-State Circuits Conference (ESSCIRC) · 8
A Novel Event-Based Method for ASK Demodulation
2022 · Alexis Rodrigo Iga Jadue, Sylvain Engels, et al. · IEEE Latin American Symposium on Circuits and Systems (LASCAS) · 6
An Event-Based Strategy for ASK demodulation
2019 · Alexis Rodrigo Iga Jadue, Sylvain Engels, et al. · International Conference on Event-based Control, Communication, and Signal Processing · 6
A fine grain variation-aware dynamic Vdd-hopping AVFS architecture on a 32nm GALS MPSoC
2013 · E. Beigne, I. Miro-Panades, et al. · European Solid-State Circuits Conference (ESSCIRC) · 6
Continuous representation of the performance of a CMOS library
2004 · B. Labouygues, J. Schindler, et al. · European Solid-State Circuits Conference (ESSCIRC) · 6
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Method for Data-Driven Pruning in Micropipeline Circuits
2023 · Cristiano Merio, Xavier Lesage, et al. · IFIP/IEEE International Conference on Very Large Scale Integration · 4
Analysis of Representative Critical Path as Delay Line for Bundled-Data Circuits
2025 · Jéssica Gonsalves Santos, Ismael de Almeida Junior, et al. · Symposium on Integrated Circuits and Systems Design · 3
A Distributed Body-Biasing Strategy for Asynchronous Circuits
2019 · L. Fesquet, Y. Decoudu, et al. · IFIP/IEEE International Conference on Very Large Scale Integration · 3
Bottom-up digital system-level reliability modeling
2011 · N. Ruiz Amador, V. Huard, et al. · Custom Integrated Circuits Conference · 3
Statistical Characterization of Library Timing Performance
2006 · V. Migairou, R. Wilson, et al. · Lecture notes in computer science · 3
A Digital Event-Based Strategy for ASK demodulation
2019 · Alexis Rodrigo IGA JADUE, Sylvain ENGELS, et al. · IFIP/IEEE International Conference on Very Large Scale Integration · 2
Event-based design strategy for circuit electromagnetic compatibility
2017 · Sophie Germain, Sylvain Engels, et al. · International Conference on Event-based Control, Communication, and Signal Processing · 2
Voltage scaling and body biasing methodology for high performance hardwired LDPC
2010 · Nabila Moubdi, Philippe Maurine, et al. · IEEE International Conference on IC Design and Technology (ICICDT) · 2
Asymmetric Current-Starved Inverter Delay Lines for High-Performance Bundled-Data Circuits
2026 · Jéssica Gonsalves Santos, Cristiano Merio, et al. · IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC) · 1
Data-driven Processing Element for Sparse Convolutional Neural Networks
2024 · Xavier Lesage, Cristiano Merio, et al. · IEEE Interregional NEWCAS Conference (NEWCAS) · 1
Clockless Design Performance Monitoring for Nanometer Technologies
2014 · Marc Renaudin, Aurelien Buhrig, et al. · IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC) · 1
On-Chip Process Variability Monitoring Flow
2010 · Nabila Moubdi, Philippe Maurine, et al. · Journal of Low Power Electronics · 1
Product On-Chip Process Compensation for Low Power and Yield Enhancement
2010 · Nabila Moubdi, Philippe Maurine, et al. · Lecture notes in computer science · 1
Works count: 56
Citation count: 267
H-index: 8
I10-index: 6
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