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Marios C. Papaefthymiou

Observed names: M Papaefthymiou, M. C. Papaefthymiou, M. Papaefthymiou, M.C. Papaefthymiou, M.M. Papaefthymiou, Marios Papaefthymiou, Papaefthymiou Marios, Papaefthymiou, Marios, Papaefthymiou, Marios C., Prof Marios Papaefthymiou
Observed institutions: University of California, Irvine, University of Michigan, Berkeley City College, Institute of Electrical and Electronics Engineers, Yale University, Cambridge Scientific (United States), IBM Research - Thomas J. Watson Research Center, Berkeley Earth, University of Rochester, Massachusetts Institute of Technology
OpenAlex ID: A5113772974
Precomputation-based sequential logic optimization for low power
1994 · M. Alidina, J. Monteiro, et al. · IEEE Transactions on Very Large Scale Integration (VLSI) Systems · 298
Computational sprinting
2012 · Arun Raghavan, Yixin Luo, et al. · IEEE International Symposium on High-Performance Computer Architecture (HPCA) · 180
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A real-time electrical load forecasting and unsupervised anomaly detection framework
2022 · Xinlin Wang, Zhihao Yao, et al. · Applied Energy · 101
Figure-of-merit for phase-change materials used in thermal management
2016 · Lei Shao, Arun Raghavan, et al. · International Journal of Heat and Mass Transfer · 101
Optimizing two-phase, level-clocked circuitry
1997 · Alexander T. Ishii, Charles E. Leiserson, et al. · Journal of the ACM · 83
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True single-phase adiabatic circuitry
2001 · Suhwan Kim, M.C. Papaefthymiou · IEEE Transactions on Very Large Scale Integration (VLSI) Systems · 82
Energy-Efficient GHz-Class Charge-Recovery Logic
2007 · Visvesh S. Sathe, Juang-Ying Chueh, et al. · IEEE Journal of Solid-State Circuits · 79
A Multi-Mode Power Gating Structure for Low-Voltage Deep-Submicron CMOS ICs
2007 · Suhwan Kim, Stephen V. Kosonocky, et al. · IEEE Transactions on Circuits and Systems II Analog and Digital Signal Processing · 70
Resonant-Clock Design for a Power-Efficient, High-Volume x86-64 Microprocessor
2012 · Visvesh S. Sathe, Srikanth Arekapudi, et al. · IEEE Journal of Solid-State Circuits · 68
Charge-Recovery Computing on Silicon
2005 · Suhwan Kim, C.H. Ziesler, et al. · IEEE Transactions on Computers · 68
Computational sprinting on a hardware/software testbed
2013 · Arun Raghavan, Laurel Emurian, et al. · International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS) · 58
Block-based multiperiod dynamic memory design for low data-retention power
2003 · Joohee Kim, M.C. Papaefthymiou · IEEE Transactions on Very Large Scale Integration (VLSI) Systems · 56
Low power parallel multiplier design for DSP applications through coefficient optimization
2003 · Sangjin Hong, Suhwan Kim, et al. · Annual IEEE International ASIC Conference and Exhibit · 51
True single-phase energy-recovering logic for low-power, high-speed VLSI
1998 · S. Kim, M.C. Papaefthymiou · International Symposium on Low Power Electronics and Design (ISLPED) · 51
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Understanding retiming through maximum average-weight cycles
1991 · Marios C. Papaefthymiou · ACM Symposium on Parallelism in Algorithms and Architectures (SPAA) · 48
DELAY
1995 · Kumar N. Lalgudi, Marios C. Papaefthymiou · ACM/IEEE Design Automation Conference (DAC) · 47
Resonant-Clock Latch-Based Design
2008 · Visvesh S. Sathe, Jerry C. Kao, et al. · IEEE Journal of Solid-State Circuits · 43
A true single-phase energy-recovery multiplier
2003 · Suhwan Kim, C.H. Ziesler, et al. · IEEE Transactions on Very Large Scale Integration (VLSI) Systems · 43
Analytical macromodeling for high-level power estimation
1999 · Guiseppe Bernacchia, Marios C. Papaefthymiou · 43
Single-phase source-coupled adiabatic logic
1999 · Suhwan Kim, M.C. Papaefthymiou · International Symposium on Low Power Electronics and Design (ISLPED) · 43
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On-chip phase change heat sinks designed for computational sprinting
2014 · Lei Shao, Arun Raghavan, et al. · Annual IEEE Semiconductor Thermal Measurement and Management Symposium/Proceedings · 42
Utilizing Dark Silicon to Save Energy with Computational Sprinting
2013 · Arun Raghavan, Laurel Emurian, et al. · IEEE Micro · 40
Precomputation-based sequential logic optimization for low power
1994 · M. Alidina, José Monteiro, et al. · DSpace@MIT (Massachusetts Institute of Technology) · 40
1.32GHz high-throughput charge-recovery AES core with resistance to DPA attacks
2015 · Shengshuo Lu, Zhengya Zhang, et al. · Symposium on VLSI Circuits · 38
Retiming and clock scheduling for digital circuit optimization
2002 · Xun Liu, M.C. Papaefthymiou, et al. · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · 38
Works count: 173
Citation count: 3,086
H-index: 30
I10-index: 75
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