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A. Murali

Observed names: Alenkruth Krishnan Murali, Murali A, Murali, Alenkruth Krishnan
OpenAlex ID: A5113929382
Improved design debugging architecture using low power serial communication protocols for signal processing applications
2021 · A. Murali, Hari Kishore Kakarla, et al. · International Journal of Speech Technology · 24
Efficient and high speed key-independent AES-based authenticated encryption architecture using FPGAs
2017 · A. Murali, K Hari Kishore · International Journal of Engineering & Technology · 14
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Integrating the Reconfigurable Devices Using Slow-Changing Key Technique to Achieve High Performance
2017 · A. Murali, K. Hari Kishore, et al. · IEEE International Advance Computing Conference · 13
Hybrid current mirror-voltage latch sense amplifier with offset correction for enhanced yield in process-sensitive SRAM
2025 · Chokkakula Ganesh, A. Murali, et al. · Results in Engineering · 4
VLSI design for efficient RSD-Based ECC processor using Karatsuba algorithm
2017 · Pasluri Bindu Swetha, V.J. Kishore Sonti, et al. · International Journal of Engineering & Technology · 3
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Integrated and effective in-system debugging approach in FPGA circuits
2017 · A. Murali, K. Hari Kishore · International Journal of Engineering & Technology · 2
Implementation of Reconfigurable Circuit with Watch-Points in the Hardware
2017 · A. Murali, K. Hari Kishore, et al. · Lecture notes in electrical engineering · 2
Comparative Performance Analysis of Low Power Full Adder Design in Different Logics in 22nm Scaling Technology
2016 · Murali A, Santosh Kumar L.V, et al. · International Journal on Cybernetics & Informatics · 2
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SoK: ARCUS: On the Efficiency and Efficacy of Hardware Fuzzing
2026 · Murali, Alenkruth Krishnan, Saravanan, Raghul, et al. · arXiv (Cornell University) · 1
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Design And Implementation of Hybrid Memory Logic Built-In Self-Test Architecture
2025 · Chokkakula Ganesh, A. Murali, et al. · Advances in computer science research · 1
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Design of Scan Cell for System on Chip Scan Based Debugging Applications
2017 · A. Murali, K. Hari Kishore, et al. · Lecture notes in networks and systems · 1
Improved In-System Debugging of High Level Synthesis Generated FPGA Circuits
2017 · A. Murali, K. Hari Kishore, et al. · Lecture notes in networks and systems · 1
Article Type: Conference Proceeding Enhanced Implementation of Efficient AES based Algorithm on FPGA
2014 · A. Murali, B. N. Mohan Kumar, et al.
Works count: 14
Citation count: 68
H-index: 4
I10-index: 3
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