Author

K. R. Vinay Kumar

Institution: R.V. College of Engineering

Observed institution: R.V. College of Engineering

OpenAlex ID: A5147911041

FPGA validated RISC V system on chip with a custom systolic array accelerator for edge AI inference

2026 · Srujan Sateesh Kalagi, K. R. Vinay Kumar, et al. · Discover Artificial Intelligence

Works count: 1

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