Author

Supreetha Rao

Institution: Visvesvaraya Technological University

Observed institution: Visvesvaraya Technological University

OpenAlex ID: A5148064310

FPGA-Based Design and Verification of a Hazard-Aware Pipelined RISC-V Processor with an Optimized APB Interface for Ethernet Applications

2026 · Supreetha Rao, Satish Bhairannawar · Chips

Optimized Pipelined RISC-V Processor with Data Hazard Detection for Verification of Ethernet Controller

2026 · Supreetha Rao, Satish Bhairannawar · International Journal of Computer Information Systems and Industrial Management Applications

Works count: 2

Citation count:

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