Collaborative Research: DESC: Type II: REFRESH: Revisiting Expanding FPGA Real-estate for Environmentally Sustainability Heterogeneous-Systems
Description: Computing systems can exert substantial environmental impacts across their entire life cycles, encompassing manufacturing, usage, and end-of-life disposal. For example, manufacturing processes often require significant amounts of energy and produce substantial carbon emissions. When computers reach the end of their life, they become electronic waste (e-waste). E-waste, if not properly managed, can pose risks to human health and the environment due to the presence of hazardous materials. Mitigating these impacts is a significant challenge for sustainable computing. This project introduces innovative approaches to minimize the environmental impact of computing systems by recycling decommissioned chips, integrating them to extend their lifespans, and achieving near state-of-the-art performance with the newly integrated chips. The project will be carried out by a team of investigators from the University of Pittsburgh and the University of Notre Dame. The project's impacts are twofold: significantly reducing carbon emissions from manufacturing and mitigating environmental risks associated with e-waste by keeping these toxic, non-biodegradable devices out of landfills. This project is making valuable contributions to society through education and outreach activities designed to engage K-12 students with an interest in environmental science, biology, and artificial intelligence (AI).
The primary goal of this project is to achieve sustainable computing by reusing recently retired field-programmable gate array (FPGA) chips to build REFRESH FPGA devices and employing 2.5-dimensional (2.5D) integration with an underlying interposer for interconnection. This approach aims to significantly reduce carbon emissions incurred from the fabrication process of new chips. The project consists of four research thrusts. Thrust 1 focuses on developing REFRESH FPGA architecture and design automation toolflow, tailored to address the challenge of targeting hardware designs onto non-monolithic FPGAs. Thrust 2 investigates REFRESH FPGA hardware analysis and prototyping through a design automation framework capable of automatically selecting the optimal design configuration including inter-chip connection topology, connection bandwidth, and the selection of FPGA chips based on their aging condition. Thrust 3 is dedicated to developing a system-in-a-package sustainability analysis, validation, and optimization process, aiming to accurately model and assess the environmental impacts stemming from the 2.5D integrated REFRESH FPGAs including fabrication, integration, and packaging. Thrust 4 extensively explores the most effective methodologies for accelerating a wide range of applications from machine learning to genomics.
This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.
Funder: National Science Foundation
Amount: $1,500,000
Funding type: grant
Funder scheme: Standard Grant
Start date: 2023-10-01
End date: 2025-08-31
Investigator: Peipei Zhou
Institution: University of Pittsburgh
Funded outputs count: 9
Funder award ID: 2324864
OpenAlex ID: G3182206366