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Keyword

arithmetic logic unit

Description: An arithmetic logic unit is a digital circuit in a processor that performs arithmetic and bitwise operations on binary data.
Wikidata ID: wiki/Q192903
OpenAlex ID: keywords/arithmetic-logic-unit
Digital arithmetic
2003 · Miloš D. Ercegovac, Toms Lang · 586
High-speed compact circuits with CMOS
1982 · R.H. Krambeck, C.M. Lee, et al. · IEEE Journal of Solid-State Circuits · 471
Monolithic optical microlithography of high-density elastic circuits
2021 · Yu-Qing Zheng, Yuxin Liu, et al. · Science · 402
Benchmarking of Beyond-CMOS Exploratory Devices for Logic Integrated Circuits
2015 · Dmitri E. Nikonov, Ian A. Young · IEEE Journal on Exploratory Solid-State Computational Devices and Circuits · 349
Concurrent Error Detection in ALU's by Recomputing with Shifted Operands
1982 · Patel, Fung · IEEE Transactions on Computers · 335
The Stratix II logic and routing architecture
2005 · David Lewis, Elias Ahmed, et al. · ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA) · 220
A 1.5-ns 32-b CMOS ALU in double pass-transistor logic
1993 · M. Suzuki, N. Ohkubo, et al. · IEEE Journal of Solid-State Circuits · 204
A reconfigurable arithmetic array for multimedia applications
1999 · Alan Marshall, Tony Stansfield, et al. · ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA) · 170
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Electronic-photonic arithmetic logic unit for high-speed computing
2020 · Zhoufeng Ying, Chenghao Feng, et al. · Nature Communications · 159
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Design of Power Aware on Chip Embedded Memory based FSM Encoding in FPGA
2015 · M. Jasmin, T. Vigneshwaran, et al. · Indian Journal of Science and Technology · 135
Edge-valued binary decision diagrams for multi-level hierarchical verification
1992 · Yung-Te Lai, S. Sastry · 134
Designing Efficient Circuits Based on Runtime-Reconfigurable Field-Effect Transistors
2018 · Shubham Rai, Jens Trommer, et al. · IEEE Transactions on Very Large Scale Integration (VLSI) Systems · 121
Carry checking/parity prediction adders and ALUs
2003 · M. Nicolaidis · IEEE Transactions on Very Large Scale Integration (VLSI) Systems · 120
Supercomputing with spin-polarized single electrons in a quantum coupled architecture
1994 · S Bandyopadhyay, B Das, et al. · Nanotechnology · 118
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Dynamics of nuclear reactors
1972 · Sam E. Berk · Journal of the Franklin Institute · 118
Design and Implementation of a Pipelined Bit-Serial SFQ Microprocessor, ${\rm CORE}1\beta$
2007 · Y. Yamanashi, M. Tanaka, et al. · IEEE Transactions on Applied Superconductivity · 111
20GHz Operation of an Asynchronous Wave-Pipelined RSFQ Arithmetic-Logic Unit
2012 · Timur V. Filippov, Anubhav Sahu, et al. · Physics Procedia · 107
Design of an Efficient Multilayer Arithmetic Logic Unit in Quantum-Dot Cellular Automata (QCA)
2018 · Shahram Babaie, Ali Sadoghifar, et al. · IEEE Transactions on Circuits & Systems II Express Briefs · 106
Design of a Reversible ALU Based on Novel Programmable Reversible Logic Gate Structures
2011 · Matthew Morrison, Nagarajan Ranganathan · IEEE Computer Society Annual Symposium on VLSI · 105
Efficient implementations of self-checking adders and ALUs
2002 · M. Nicolaidis · 99
Introduction to computer architecture
2018 · Joseph D. Dumas II, Joseph D. Dumas II · CRC Press eBooks · 97
Design of a practical fault-tolerant adder in QCA
2016 · Dharmendra Kumar, Debasis Mitra · Microelectronics Journal · 85
Magnetic Tunnel Junction-Based Spintronic Logic Units Operated by Spin Transfer Torque
2011 · Xiaofeng Yao, Jonathan Harms, et al. · IEEE Transactions on Nanotechnology · 82
The design and implementation of a robust single-layer QCA ALU using a novel fault-tolerant three-input majority gate
2020 · Seyed-Sajad Ahmadpour, Mohammad Mosleh, et al. · The Journal of Supercomputing · 81
A spintronics full adder for magnetic CPU
2005 · Hao Meng, Jianguo Wang, et al. · IEEE Electron Device Letters · 80
Works count: 3,514
Citation count: 17,060
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