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Keyword

chip stacking

Description: Chip stacking is a semiconductor packaging technique that vertically integrates multiple integrated-circuit dies to increase device density and interconnection.
OpenAlex ID: keywords/chip-stacking
Design and Management of 3D Chip Multiprocessors Using Network-in-Memory
2006 · Feihui Li, Chrysostomos Nicopoulos, et al. · ACM SIGARCH Computer Architecture News · 383
A review of 3-D packaging technology
1998 · S.F. Al-Sarawi, D. Abbott, et al. · IEEE Transactions on Components Packaging and Manufacturing Technology Part B · 383
Handbook of 3D Integration
2008 · Wiley eBooks · 364
Processor Design in 3D Die-Stacking Technologies
2007 · Gabriel H. Loh, Yuan Xie, et al. · IEEE Micro · 292
Handbook of 3D integration : technology and applications of 3D integrated circuits
2012 · Philip E. Garrou, Christopher A. Bower, et al. · 226
3-D Silicon Integration and Silicon Packaging Technology Using Silicon Through-Vias
2006 · J.U. Knickerbocker, C.S. Patel, et al. · IEEE Journal of Solid-State Circuits · 185
Current Status of Research and Development for Three-Dimensional Chip Stack Technology
2001 · Kenji Takahashi Kenji Takahashi, Hiroshi Terao Hiroshi Terao, et al. · Japanese Journal of Applied Physics · 175
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TSV Redundancy: Architecture and Design Issues in 3-D IC
2011 · Ang-Chih Hsieh, TingTing Hwang · IEEE Transactions on Very Large Scale Integration (VLSI) Systems · 138
Monolithic 3D Integrated Circuits
2007 · Simon Wong, Abbas El-Gamal, et al. · International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA) · 105
Rapid fabrication of a four-layer PMMA-based microfluidic chip using CO 2 -laser micromachining and thermal bonding
2016 · Xueye Chen, Jienan Shen, et al. · Journal of Micromechanics and Microengineering · 104
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Full intermetallic joints for chip stacking by using thermal gradient bonding
2016 · T.L. Yang, T. Aoki, et al. · Acta Materialia · 102
A Review of Recent Advances in Thermal Management in Three Dimensional Chip Stacks in Electronic Systems
2011 · Vikram Venkatadri, Bahgat Sammakia, et al. · Journal of Electronic Packaging · 95
Intermetallic compounds in 3D integrated circuits technology: a brief review
2017 · Syahira Annuar, Reza Mahmoodian, et al. · Science and Technology of Advanced Materials · 88
3D Integration technology: Status and application development
2010 · Peter Ramm, Armin Klumpp, et al. · Proceedings of ESSCIRC · 83
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Forced convective interlayer cooling in vertically integrated packages
2008 · Thomas Brunschwiler, B. Michel, et al. · I-THERM :/I-THERM - Intersociety Conference on Thermal Phenomena in Electronic Systems · 83
3D packaging: where all technologies come together
2004 · M. Karnezos · IEEE/CPMT/SEMI International Electronics Manufacturing Technology Symposium (IEMT) · 79
Process integration for through-silicon vias
2005 · S. Spiesshoefer, Z. Rahman, et al. · Journal of Vacuum Science & Technology A Vacuum Surfaces and Films · 77
Three-dimensional integration: An industry perspective
2015 · Subramanian S. Iyer · MRS Bulletin · 69
Design and Management of 3D Chip Multiprocessors Using Network-in-Memory
2006 · Feihui Li, C. Nicopoulos, et al. · Proceedings - International Symposium on Computer Architecture/Proceedings · 69
Overcoming research challenges for CMOS scaling: industry directions
2006 · Tze-chiang Chen · International Conference on Solid-State and Integrated Circuit Technology (ICSICT) · 67
Fabrication of High Aspect Ratio TSV and Assembly With Fine-Pitch Low-Cost Solder Microbump for Si Interposer Technology With High-Density Interconnects
2011 · Aibin Yu, John H. Lau, et al. · IEEE Transactions on Components Packaging and Manufacturing Technology · 66
3D Integration for NoC-based SoC Architectures
2010 · Abbas Sheibanyrad, Frédéric Pétrot, et al. · Integrated circuits and systems · 66
Topology-Aware Adaptive Routing for Nonstationary Irregular Mesh in Throttled 3D NoC Systems
2012 · Kun-Chih Chen, Shu-Yen Lin, et al. · IEEE Transactions on Parallel and Distributed Systems · 65
Design and verification of a thermoelectric energy harvester with stacked polysilicon thermocouples by CMOS process
2009 · S.M. Yang, T. Lee, et al. · Sensors and Actuators A Physical · 56
Enabling technologies for 3D integration: From packaging miniaturization to advanced stacked ICs
2008 · N. Sillon, A. Astier, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 56
Works count: 962
Citation count: 7,837
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