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Keyword

drive current

Description: The electrical current supplied to a semiconductor device, such as a transistor or memory cell, to control its operation.
OpenAlex ID: keywords/drive-current
Double-Gate Tunnel FET With High- Gate Dielectric
2007 · Kathy Boucart, Adrian Mihai Ionescu · IEEE Transactions on Electron Devices · 1,661
Low-Voltage Tunnel Transistors for Beyond CMOS Logic
2010 · Alan C. Seabaugh, Qin Zhang · Proceedings of the IEEE · 1,637
Ge/Si nanowire heterostructures as high-performance field-effect transistors
2006 · Jie Xiang, Wei Lu, et al. · Nature · 1,450
Electrolyte‐Gated Transistors for Organic and Printed Electronics
2012 · Se Hyun Kim, Kihyon Hong, et al. · Advanced Materials · 956
A 45nm Logic Technology with High-k+Metal Gate Transistors, Strained Silicon, 9 Cu Interconnect Layers, 193nm Dry Patterning, and 100% Pb-free Packaging
2007 · K. Mistry, R. Chau, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 854
Fully Transparent ZnO Thin‐Film Transistor Produced at Room Temperature
2005 · E. M. C. Fortunato, P. M. C. Barquinha, et al. · Advanced Materials · 840
A 22nm high performance and low-power CMOS technology featuring fully-depleted tri-gate transistors, self-aligned contacts and high density MIM capacitors
2012 · C. Auth, C. Allen, et al. · Symposium on VLSI Technology · 781
The Role of Metal−Nanotube Contact in the Performance of Carbon Nanotube Field-Effect Transistors
2005 · Zhihong Chen, Joerg Appenzeller, et al. · Nano Letters · 671
High-performance fully depleted silicon nanowire (diameter /spl les/ 5 nm) gate-all-around CMOS devices
2006 · N. Singh, A. Agarwal, et al. · IEEE Electron Device Letters · 644
MoS2 P-type Transistors and Diodes Enabled by High Work Function MoOx Contacts
2014 · Steven Chuang, Corsin Battaglia, et al. · Nano Letters · 575
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A 14nm logic technology featuring 2nd-generation FinFET, air-gapped interconnects, self-aligned double patterning and a 0.0588 µm2 SRAM cell size
2014 · S. Natarajan, M. Agostinelli, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 543
Thin Film Nanotube Transistors Based on Self-Assembled, Aligned, Semiconducting Carbon Nanotube Arrays
2008 · Michael Engel, Joshua P. Small, et al. · ACS Nano · 511
Double-Gate Strained-Ge Heterostructure Tunneling FET (TFET) With record high drive currents and ≪60mV/dec subthreshold slope
2008 · Tejas Krishnamohan, Donghyun Kim, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 496
Novel Attributes of a Dual Material Gate Nanoscale Tunnel Field-Effect Transistor
2011 · Sneh Saurabh, M. Jagadesh Kumar · IEEE Transactions on Electron Devices · 470
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High performance fully-depleted tri-gate CMOS transistors
2003 · B.S. Doyle, S. Datta, et al. · IEEE Electron Device Letters · 453
Tunnel field-effect transistor without gate-drain overlap
2007 · Anne S. Verhulst, William G. Vandenberghe, et al. · Applied Physics Letters · 429
InAs/InP Radial Nanowire Heterostructures as High Electron Mobility Devices
2007 · Xiaocheng Jiang, Qihua Xiong, et al. · Nano Letters · 387
A 10nm high performance and low-power CMOS technology featuring 3 rd generation FinFET transistors, Self-Aligned Quad Patterning, contact over active gate and cobalt local interconnects
2017 · C. Auth, A. Aliyarukunju, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 384
Carbon Nanotubes for High-Performance Electronics—Progress and Prospect
2008 · J. Appenzeller · Proceedings of the IEEE · 379
Graphene Transistors Fabricated via Transfer-Printing In Device Active-Areas on Large Wafer
2007 · Xiaogan Liang, Zengli Fu, et al. · Nano Letters · 361
The Tunnel Source (PNPN) n-MOSFET: A Novel High Performance Transistor
2008 · Venkatagirish Nagavarapu, Ritesh Jhaveri, et al. · IEEE Transactions on Electron Devices · 354
Fabrication, characterization, and physics of III–V heterojunction tunneling Field Effect Transistors (H-TFET) for steep sub-threshold swing
2011 · G. Dewey, B. Chu-Kung, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 339
Demonstration of L-Shaped Tunnel Field-Effect Transistors
2015 · Sang Wan Kim, Jang Hyun Kim, et al. · IEEE Transactions on Electron Devices · 336
A 22nm SoC platform technology featuring 3-D tri-gate and high-k/metal gate, optimized for ultra low power, high performance and high density SoC applications
2012 · C.-H. Jan, U. Bhattacharya, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 310
A Numerical Study of Scaling Issues for Schottky-Barrier Carbon Nanotube Transistors
2004 · J. Guo, S. Datta, et al. · IEEE Transactions on Electron Devices · 307
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Works count: 3,714
Citation count: 66,460
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