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FinFET
Description:
A field-effect transistor with a fin-shaped semiconductor channel, used in integrated circuits to improve control of current flow.
Primary topic:
Advancements in Semiconductor Devices and Circuit Design (44%)
Related topics:
Advancements in Semiconductor Devices and Circuit Design (44%),
Low-power high-performance VLSI design (16%),
Semiconductor materials and devices (8%)
Wikidata ID:
wiki/Q33114556
OpenAlex ID:
keywords/finfet
FinFET-a self-aligned double-gate MOSFET scalable to 20 nm
2000
·
Chenming Hu
, J. Bokor
, et al.
·
IEEE Transactions on Electron Devices
·
1,660
FinFETs and Other Multi-Gate Transistors
2007
·
Jean-Pierre Colinge
·
Springer eBooks
·
1,137
ASAP7: A 7-nm finFET predictive process design kit
2016
·
Lawrence T. Clark
, Vinay Vashishtha
, et al.
·
Microelectronics Journal
·
780
PDF
Fundamentals of Modern VLSI Devices
2021
·
Yuan Taur
, Tak H. Ning
·
Cambridge University Press eBooks
·
754
Heat Generation and Transport in Nanometer-Scale Transistors
2006
·
E. Pop
, S. Sinha
, et al.
·
Proceedings of the IEEE
·
696
Considerations for Ultimate CMOS Scaling
2012
·
K. J. Kuhn
·
IEEE Transactions on Electron Devices
·
680
The future transistors
2023
·
Wei Cao
, Huiming Bu
, et al.
·
Nature
·
626
FinFET scaling to 10 nm gate length
2003
·
Bin Yu
, Leland Chang
, et al.
·
596
A 14nm logic technology featuring 2nd-generation FinFET, air-gapped interconnects, self-aligned double patterning and a 0.0588 µm2 SRAM cell size
2014
·
S. Natarajan
, M. Agostinelli
, et al.
·
Technical digest - International Electron Devices Meeting/Technical digest
·
543
Review of: "FinFET nanotransistor downscaling causes more short channel effects, less gate control, exponential increase in leakage currents, drastic process changes and unmanageable power densities"
2024
·
Afshin Rashid
·
Qeios
·
501
PDF
Review of: "FinFET nanotransistor, the reduction of scale causes more short channel effects, less gate control, an exponential increase in leakage currents, severe process changes, and power densities"
2024
·
Chad Allen
·
Qeios
·
462
PDF
Turning silicon on its edge
2004
·
E.J. Nowak
, I. Aller
, et al.
·
IEEE Circuits and Devices Magazine
·
389
A 10nm high performance and low-power CMOS technology featuring 3 rd generation FinFET transistors, Self-Aligned Quad Patterning, contact over active gate and cobalt local interconnects
2017
·
C. Auth
, A. Aliyarukunju
, et al.
·
Technical digest - International Electron Devices Meeting/Technical digest
·
384
Strain: A Solution for Higher Carrier Mobility in Nanoscale MOSFETs
2009
·
Min Chu
, Yongke Sun
, et al.
·
Annual Review of Materials Research
·
377
Sub 50-nm FinFET: PMOS
2003
·
Xuejue Huang
, Wen-Chin Lee
, et al.
·
Technical digest - International Electron Devices Meeting/Technical digest
·
371
Donor deactivation in silicon nanostructures
2009
·
Mikael T. Björk
, Heinz Schmid
, et al.
·
Nature Nanotechnology
·
332
Exploring sub-20nm FinFET design with predictive technology models
2012
·
Saurabh Sinha
, Greg Yeric
, et al.
·
Proceedings - ACM IEEE Design Automation Conference
·
325
22nm FDSOI technology for emerging mobile, Internet-of-Things, and RF applications
2016
·
R. Carter
, J. Mazurier
, et al.
·
Technical digest - International Electron Devices Meeting/Technical digest
·
300
FinFET design considerations based on 3-D simulation and analytical modeling
2002
·
G. Pei
, J. Kedzierski
, et al.
·
IEEE Transactions on Electron Devices
·
296
Challenges and Limitations of CMOS Scaling for FinFET and Beyond Architectures
2019
·
Ali Razavieh
, Peter Zeitzoff
, et al.
·
IEEE Transactions on Nanotechnology
·
291
Sub-50 nm P-channel FinFET
2001
·
Xuejue Huang
, Wen-Chin Lee
, et al.
·
IEEE Transactions on Electron Devices
·
284
Extremely scaled silicon nano-CMOS devices
2003
·
Leland Chang
, Yang-Kyu Choi
, et al.
·
Proceedings of the IEEE
·
280
Statistical variability and reliability in nanoscale FinFETs
2011
·
Xingsheng Wang
, Andrew R. Brown
, et al.
·
Technical digest - International Electron Devices Meeting/Technical digest
·
279
Nanoscale FinFETs with gate-source/drain underlap
2004
·
V. Trivedi
, J.G. Fossum
, et al.
·
IEEE Transactions on Electron Devices
·
271
The Complementary FET (CFET) for CMOS scaling beyond N3
2018
·
J. Ryckaert
, P. Schuddinck
, et al.
·
IEEE Symposium on VLSI Technology
·
255
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Works count:
9,342
Citation count:
90,010
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