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Keyword

floating-point unit

Description: A floating-point unit is a processor component that performs arithmetic operations on floating-point numbers in computer systems.
Wikidata ID: wiki/Q733507
OpenAlex ID: keywords/floating-point-unit
MIPS RISC architecture
1988 · Gerry Kane, Joe Heinrich · CERN Document Server (European Organization for Nuclear Research) · 554
Microarchitectural techniques for power gating of execution units
2004 · Zhigang Hu, Alper Buyuktosunoglu, et al. · International Symposium on Low Power Electronics and Design (ISLPED) · 396
A 200-MHz 64-b dual-issue CMOS microprocessor
1992 · D.W. Dobberpuhl, R.T. Witek, et al. · IEEE Journal of Solid-State Circuits · 392
Design of the IBM RISC System/6000 floating-point execution unit
1990 · R. K. Montoye, E. Hokenek, et al. · IBM Journal of Research and Development · 186
Bambu: A modular framework for the high level synthesis of memory-intensive applications
2013 · Christian Pilato, Fabrizio Ferrandi · International Conference on Field Programmable Logic and Applications (FPL) · 144
Evaluating the Imagine Stream Architecture
2004 · Jung Ho Ahn, William J. Dally, et al. · ACM SIGARCH Computer Architecture News · 129
Energy-Efficient Floating-Point Unit Design
2010 · Sameh Galal, Mark Horowitz · IEEE Transactions on Computers · 128
FPnew: An Open-Source Multiformat Floating-Point Unit Architecture for Energy-Proportional Transprecision Computing
2021 · Mach S., Schuiki F., et al. · Archivio istituzionale della ricerca (Alma Mater Studiorum Università di Bologna) · 120
Second-generation RISC floating point with multiply-add fused
1990 · E. Hokenek, R.K. Montoye, et al. · IEEE Journal of Solid-State Circuits · 119
UltraSPARC T2: A highly-treaded, power-efficient, SPARC SOC
2007 · Manish Shah, Christopher Olson, et al. · IEEE Asian Solid-State Circuits Conference (A-SSCC) · 107
Parameterized Posit Arithmetic Hardware Generator
2018 · Rohit Chaurasiya, John Gustafson, et al. · Proceedings, IEEE International Conference on Computer Design/Proceedings - IEEE International Conference on Computer Design · 104
Floating point unit generation and evaluation for FPGAs
2003 · Jian Liang, R. Tessier, et al. · 101
1995 high level synthesis design repository
1995 · Preeti R. Panda, Nikil D. Dutt · International Symposium on System Synthesis (ISSS) · 93
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The AMD “Zen 2” Processor
2020 · David Suggs, Mahesh Subramony, et al. · IEEE Micro · 84
Scalable and modular algorithms for floating-point matrix multiplication on FPGAs
2004 · Ling Zhuo, V.K. Prasanna · Proceedings - IEEE International Parallel and Distributed Processing Symposium · 84
Instruction Issue Logic in Pipelined Supercomputers
1984 · Weiss, Smith · IEEE Transactions on Computers · 83
Floating-Point Fused Multiply-Add Architectures
2007 · Eric Quinnell, Earl E. Swartzlander, et al. · 2018 52nd Asilomar Conference on Signals, Systems, and Computers · 81
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Division and square root: choosing the right implementation
1997 · P. Soderquist, M. Leeser · IEEE Micro · 80
Performance features of the PA7100 microprocessor
1993 · T. Asprey, G.S. Averill, et al. · IEEE Micro · 80
High-Performance Designs for Linear Algebra Operations on Reconfigurable Hardware
2008 · Ling Zhuo, Viktor K. Prasanna · IEEE Transactions on Computers · 79
Design issues in high performance floating point arithmetic units
1996 · Stuart F. Oberman · 78
The Mips R4000 processor
1992 · S. Mirapuri, M. Woodacre, et al. · IEEE Micro · 75
Embedded floating-point units in FPGAs
2006 · Michael J. Beauchamp, Scott Hauck, et al. · ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA) · 72
The SNAP project: design of floating point arithmetic units
2002 · S.F. Oberman, H. Al-Twaijry, et al. · 70
Area and performance tradeoffs in floating-point divide and square-root implementations
1996 · Peter Soderquist, Miriam Leeser · ACM Computing Surveys · 70
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Works count: 1,336
Citation count: 10,340
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