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Keyword

instruction-level parallelism

Description: A property of computer programs describing how many independent instructions can execute simultaneously while preserving correct results.
Wikidata ID: wiki/Q2714055
OpenAlex ID: keywords/instruction-level-parallelism
MediaBench: A Tool for Evaluating and Synthesizing Multimedia and Communications Systems
1997 · Chunho Lee, Miodrag Potkonjak, et al. · 2,077
Multiscalar processors
1995 · Gurindar S. Sohi, Scott E. Breach, et al. · Proceedings - International Symposium on Computer Architecture/Proceedings · 986
An Efficient Algorithm for Exploiting Multiple Arithmetic Units
1967 · R. M. Tomasulo · IBM Journal of Research and Development · 898
Software pipelining
2004 · Monica S. Lam · ACM SIGPLAN Notices · 884
Temperature-aware microarchitecture
2004 · Kevin Skadron, Mircea R. Stan, et al. · ACM Transactions on Architecture and Code Optimization · 797
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The superblock: An effective technique for VLIW and superscalar compilation
1993 · Wen -Mei W. Hwu, Scott A. Mahlke, et al. · The Journal of Supercomputing · 655
Energy dissipation in general purpose microprocessors
1996 · R. Gonzalez, M. Horowitz · IEEE Journal of Solid-State Circuits · 644
Limits of instruction-level parallelism
1991 · David W. Wall · 628
MediaBench: a tool for evaluating and synthesizing multimedia and communications systems
2002 · Chunho Lee, M. Potkonjak, et al. · 606
Error detection by duplicated instructions in super-scalar processors
2002 · N. Oh, P.P. Shirvani, et al. · IEEE Transactions on Reliability · 584
Simultaneous multithreading: Maximizing on-chip parallelism
2002 · D.M. Tullsen, S.J. Eggers, et al. · Proceedings - International Symposium on Computer Architecture/Proceedings · 564
Piranha
2000 · Luiz André Barroso, Kourosh Gharachorloo, et al. · Proceedings - International Symposium on Computer Architecture/Proceedings · 517
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Exploiting ILP, TLP, and DLP with the polymorphous TRIPS architecture
2003 · Karthikeyan Sankaralingam, Ramadass Nagarajan, et al. · Proceedings - International Symposium on Computer Architecture/Proceedings · 483
Hyper-Threading Technology Architecture and MIcroarchitecture
2002 · Deborah T. Marr · Intel Technology Journal · 474
Basic Block Distribution Analysis to Find Periodic Behavior and Simulation Points in Applications
2001 · Tim Sherwood, Erez Perelman, et al. · 474
Striped Smith–Waterman speeds database searches six times over other SIMD implementations
2006 · Michael Farrar · Bioinformatics · 416
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Pipeline Gating: Speculation Control For Energy Reduction
1998 · Srilatha Manne, Artur Klauser, et al. · 407
Simultaneous multithreading: a platform for next-generation processors
1997 · S.J. Eggers, J.S. Emer, et al. · IEEE Micro · 404
Very long instruction work architectures and the ELI-512
1998 · Joseph A. Fisher · 386
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SPARK: a high-level synthesis framework for applying parallelizing compiler transformations
2003 · S. Gupta, N. Dutt, et al. · International Conference on VLSI Design · 385
The multiflow trace scheduling compiler
1993 · P. Geoffrey Lowney, Stefan M. Freudenberger, et al. · The Journal of Supercomputing · 380
Evaluation of the Raw Microprocessor
2004 · Michael Bedford Taylor, Walter Lee, et al. · ACM SIGARCH Computer Architecture News · 354
DAISY
1997 · Kemal Ebcioğlu, Erik R. Altman · Proceedings - International Symposium on Computer Architecture/Proceedings · 349
Software pipelining
1995 · Vicki H. Allan, Reese B. Jones, et al. · ACM Computing Surveys · 347
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Instruction-level parallel processing: History, overview, and perspective
1993 · B. Ramakrishna Rau, Joseph A. Fisher · The Journal of Supercomputing · 330
Works count: 5,094
Citation count: 68,260
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