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Keyword

logic minimization

Description: Logic minimization is the process of simplifying Boolean functions or logic circuits while preserving their input-output behavior.
Wikidata ID: wiki/Q6667469
OpenAlex ID: keywords/logic-minimization
Logic Minimization Algorithms for VLSI Synthesis
1984 · Robert K. Brayton, Gary D. Hachtel, et al. · Kluwer international series in engineering and computer science · 1,972
SIS : A System for Sequential Circuit Synthesis
1992 · Ellen Sentovich · 1,870
Binary Decision Diagrams
1978 · Akers · IEEE Transactions on Computers · 1,828
Minimization of Boolean Functions*
1956 · E. J. McCluskey · Bell System Technical Journal · 1,235
MIS: A Multiple-Level Logic Optimization System
1987 · R.K. Brayton, R. Rudell, et al. · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · 1,158
The Complexity of Boolean Functions
1987 · Ingo Wegener · 888
Cascode voltage switch logic: A differential CMOS logic family
1984 · L. Heller, W. Griffin, et al. · Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference · 482
Multiple-Valued Minimization for PLA Optimization
1987 · R.L. Rudell, A. Sangiovanni-Vincentelli · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · 425
Switching Theory for Logic Synthesis
1999 · Tsutomu Sasao · Springer eBooks · 420
Multilevel logic synthesis
1990 · R.K. Brayton, G.D. Hachtel, et al. · Proceedings of the IEEE · 417
MINI: A Heuristic Approach for Logic Minimization
1974 · S. J. Hong, R. G. Cain, et al. · IBM Journal of Research and Development · 346
Optimal State Assignment for Finite State Machines
1985 · G. De Micheli, R.K. Brayton, et al. · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · 344
Minimizing the Number of States in Incompletely Specified Sequential Switching Functions
1959 · M. C. Paull, S. H. Unger · IEEE Transactions on Electronic Computers · 323
Logic synthesis for vlsi design
1989 · Richard Rudell, Alberto Sangiovanni‐Vincentelli · 297
The EPFL Combinational Benchmark Suite
2019 · Amaru, Luca, Pierre-Emmanuel Gaillardon, et al. · Infoscience (Ecole Polytechnique Fédérale de Lausanne) · 285
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On the Decomposition of Switching Functions
1961 · Sze-Tsen Hu · Defense Technical Information Center (DTIC) · 280
Logic Synthesis and Optimization
1993 · Kluwer international series in engineering and computer science · 267
The transduction method-design of logic networks based on permissible functions
1989 · S. Muroga, Y. Kambayashi, et al. · IEEE Transactions on Computers · 260
A Survey of Optimization Techniques Targeting Low Power VLSI Circuits
1995 · Srinivas Devadas, Sharad Malik · Proceedings - ACM IEEE Design Automation Conference · 250
Contemporary Logic Design
1993 · Randy H. Katz · CERN Document Server (European Organization for Nuclear Research) · 238
FPGA-Based System Design
2004 · Wayne Wolf · CERN Document Server (European Organization for Nuclear Research) · 229
Majority-Inverter Graph: A New Paradigm for Logic Optimization
2015 · Luca Amaru, Pierre-Emmanuel Gaillardon, et al. · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · 220
Recursive learning: a new implication technique for efficient solutions to CAD problems-test, verification, and optimization
1994 · W. Kunz, D.K. Pradhan · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · 214
Key management for secure lnternet multicast using Boolean function minimization techniques
1999 · I. Chang, R. Engel, et al. · 206
XTRACT
2000 · Minos Garofalakis, Aristides Gionis, et al. · ACM SIGMOD Record · 201
Works count: 3,789
Citation count: 38,070
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