Keyword

redistribution layer

Description: A conductive layer in semiconductor packaging that reroutes chip contacts to new positions for connection to package terminals or other components.

Primary topic: 3D IC and TSV technologies (58%)

Wikidata ID: wiki/Q7305977

OpenAlex ID: keywords/redistribution-layer

High-Frequency Scalable Electrical Model and Analysis of a Through Silicon Via (TSV)

2011 · Joohee Kim, Jun So Pak, et al. · IEEE Transactions on Components Packaging and Manufacturing Technology · 502

Overview and outlook of through‐silicon via (TSV) and 3D integrations

2011 · John H. Lau · Microelectronics International · 348

Embedded Wafer Level Ball Grid Array (eWLB)

2008 · T. Meyer, G. Ofner, et al. · IEEE Electronics Packaging Technology Conference (EPTC) · 246

Recent Advances and Trends in Fan-Out Wafer/Panel-Level Packaging

2019 · John H. Lau · Journal of Electronic Packaging · 127

Design and optimization of thermo-mechanical reliability in wafer level packaging

2010 · X.J. Fan, B. Varia, et al. · Microelectronics Reliability · 106

CoWoS Architecture Evolution for Next Generation HPC on 2.5D System in Package

2023 · Yu-Chen Hu, Yu-Min Liang, et al. · 2022 IEEE 72nd Electronic Components and Technology Conference (ECTC) · 104

Fully Integrated 2D Scalable TX/RX Chipset for D-Band Phased-Array-on-Glass Modules

2022 · Mohamed Elkhouly, Jaegeun Ha, et al. · Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference · 102

Design, Materials, Process, Fabrication, and Reliability of Fan-Out Wafer-Level Packaging

2018 · John H. Lau, Ming Li, et al. · IEEE Transactions on Components Packaging and Manufacturing Technology · 100

Fan-Out Wafer-Level Packaging for Heterogeneous Integration

2018 · John H. Lau, Ming Li, et al. · IEEE Transactions on Components Packaging and Manufacturing Technology · 94

Wafer Warpage Experiments and Simulation for Fan-Out Chip on Substrate

2016 · Yuan-Ting Lin, Wei-Hong Lai, et al. · 2022 IEEE 72nd Electronic Components and Technology Conference (ECTC) · 90

Embedded wafer level ball grid array (eWLB) technology for millimeter-wave applications

2011 · M. Wojnowski, R. Lachner, et al. · IEEE Electronics Packaging Technology Conference (EPTC) · 89

Heterogeneous Integrations

2019 · John H. Lau · Springer eBooks · 86

Experimental Verification and Optimization Analysis of Warpage for Panel-Level Fan-Out Package

2017 · Fengze Hou, Tingyu Lin, et al. · IEEE Transactions on Components Packaging and Manufacturing Technology · 84

Thermo-mechanical reliability of glass substrate and Through Glass Vias (TGV): A comprehensive review

2024 · Yangyang Lai, Ke Pan, et al. · Microelectronics Reliability · 81

Electromigration in three-dimensional integrated circuits

2023 · Zesheng Shen, Siyi Jing, et al. · Applied Physics Reviews · 78

A Wideband mmWave Antenna in Fan-Out Wafer Level Packaging With Tall Vertical Interconnects for 5G Wireless Communication

2021 · Bin Yu, Zhanyi Qian, et al. · IEEE Transactions on Antennas and Propagation · 74

Modeling and analysis of coupling between TSVs, metal, and RDL interconnects in TSV-based 3D IC with silicon interposer

2009 · Kihyun Yoon, Gawon Kim, et al. · IEEE Electronics Packaging Technology Conference (EPTC) · 73

High density 3D integration using CMOS foundry technologies for 28 nm node and beyond

2010 · J.C. Lin, W.C. Chiou, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 70

Synergistic effect of electromigration and Joule heating on system level weak-link failure in 2.5D integrated circuits

2015 · Yingxia Liu, Menglu Li, et al. · Journal of Applied Physics · 65

InFO_AiP Technology for High Performance and Compact 5G Millimeter Wave System Integration

2018 · Chuei-Tang Wang, Tzu-Chun Tang, et al. · 2022 IEEE 72nd Electronic Components and Technology Conference (ECTC) · 64

A Review of Polymer Dielectrics for Redistribution Layers in Interposers and Package Substrates

2023 · Pratik Nimbalkar, Pragna Bhaskar, et al. · Polymers · 61

PDF

Fan-Out Wafer and Panel Level Packaging as Packaging Platform for Heterogeneous Integration

2019 · Tanja Braun, Karl-Friedrich Becker, et al. · Micromachines · 59

PDF

Advanced low profile PoP solution with embedded wafer level PoP (eWLB-PoP) technology

2012 · Seung Wook Yoon, Jose Alvin Caparas, et al. · 2022 IEEE 72nd Electronic Components and Technology Conference (ECTC) · 59

Redistribution Layers (RDLs) for 2.5D/3D IC Integration

2014 · J. Lau, P. Tzeng, et al. · Journal of Microelectronics and Electronic Packaging · 57

Chip-First Fan-Out Panel-Level Packaging for Heterogeneous Integration

2018 · Cheng-Ta Ko, Henry Yang, et al. · IEEE Transactions on Components Packaging and Manufacturing Technology · 55

Works count: 1,880

Citation count: 12,950