Keyword

routability

Description: In electronic design automation, routability is the degree to which circuit connections can be physically routed through a chip layout.

Primary topic: VLSI and FPGA Design Techniques (86%)

OpenAlex ID: keywords/routability

Architecture of field-programmable gate arrays

1993 · J. Rose, A. El Gamal, et al. · Proceedings of the IEEE · 324

PathFinder: A Negotiation-Based Performance-Driven Router for FPGAs

1995 · L. McMurchie, C. Ebeling · 292

Flexibility of interconnection structures for field-programmable gate arrays

1991 · J. Rose, S. Brown · IEEE Journal of Solid-State Circuits · 229

Abacus

2008 · Peter Spindler, Ulf Schlichtmann, et al. · International Symposium on Physical Design · 176

Unification of partitioning, placement and floorplanning

2005 · S.N. Adya, S. Chaturvedi, et al. · 168

A High-Performance Droplet Routing Algorithm for Digital Microfluidic Biochips

2008 · Minsik Cho, D.Z. Pan · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · 148

Pattern routing: use and theory for increasing predictability and avoiding coupling

2002 · R. Kastner, E. Bozorgzadeh, et al. · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · 145

Estimating routing congestion using probabilistic analysis

2001 · Jinan Lou, Shankar Krishnamoorthy, et al. · International Symposium on Physical Design · 145

Min-cut floorplacement

2006 · J.A. Roy, S.N. Adya, et al. · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · 141

Capo

2005 · Jarrod A. Roy, David A. Papa, et al. · International Symposium on Physical Design · 140

Estimating routing congestion using probabilistic analysis

2002 · Jinan Lou, S. Thakur, et al. · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · 137

Efficient circuit clustering for area and power reduction in FPGAs

2002 · Amit Singh, Malgorzata Marek-Sadowska · ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA) · 127

The ISPD-2011 routability-driven placement contest and benchmark suite

2011 · Natarajan Viswanathan, Charles J. Alpert, et al. · International Symposium on Physical Design · 110

BoxRouter 2.0: architecture and implementation of a hybrid and robust global router

2007 · Minsik Cho, Katrina Lu, et al. · International Conference on Computer Aided Design · 110

Mason: A Global Floorplanning Approach for VLSI Design

1986 · D.P. La Potin, S.W. Director · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · 105

A fast routability- and performance-driven droplet routing algorithm for digital microfluidic biochips

2009 · Tsung-Wei Huang, Tsung-Yi Ho · Proceedings, IEEE International Conference on Computer Design/Proceedings - IEEE International Conference on Computer Design · 103

An effective congestion driven placement framework

2002 · Ulrich Brenner, André Rohe · International Symposium on Physical Design · 96

CUGR: Detailed-Routability-Driven 3D Global Routing with Probabilistic Resource Model

2020 · Jinwei Liu, Chak-Wa Pui, et al. · Proceedings - ACM IEEE Design Automation Conference · 95

Routability driven white space allocation for fixed-die standard-cell placement

2002 · Xiaojian Yang, Bo-Kyung Choi, et al. · International Symposium on Physical Design · 93

An effective congestion-driven placement framework

2003 · U. Brenner, A. Rohe · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · 88

NCTU-GR: Efficient Simulated Evolution-Based Rerouting and Congestion-Relaxed Layer Assignment on 3-D Global Routing

2011 · Ke-Ren Dai, Wen-Hao Liu, et al. · IEEE Transactions on Very Large Scale Integration (VLSI) Systems · 87

Routing Techniques for Gate Array

1983 · B.S. Ting, Bou Nin Tien · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · 87

Routability-driven repeater block planning for interconnect-centric floorplanning

2000 · Probir Sarkar, Vivek Sundararaman, et al. · International Symposium on Physical Design · 86

PDF

Congestion minimization during placement

2000 · Maogang Wang, Xiaojian Yang, et al. · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · 86

Techniques for Fast Physical Synthesis

2007 · Charles J. Alpert, Shrirang K. Karandikar, et al. · Proceedings of the IEEE · 85

Works count: 984

Citation count: 13,000