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Keyword

SRAM

Description: Static random-access memory is a semiconductor memory that stores data in bistable circuits and retains it while power is supplied.
Wikidata ID: wiki/Q267416
OpenAlex ID: keywords/sram
Integrated Circuits Based on Bilayer MoS 2 Transistors
2012 · Han Wang, Lili Yu, et al. · Nano Letters · 1,749
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Device scaling limits of Si MOSFETs and their application dependencies
2001 · D.J. Frank, R.H. Dennard, et al. · Proceedings of the IEEE · 1,573
Modeling the effect of technology trends on the soft error rate of combinational logic
2003 · P. Shivakumar, M. Kistler, et al. · IEEE/IFIP International Conference on Dependable Systems and Networks (DSN) · 1,454
A dynamic voltage scaled microprocessor system
2000 · T.D. Burd, T.A. Pering, et al. · IEEE Journal of Solid-State Circuits · 927
A durable and energy efficient main memory using phase change memory technology
2009 · Ping Zhou, Bo Zhao, et al. · Proceedings - International Symposium on Computer Architecture/Proceedings · 871
NeuroSim: A Circuit-Level Macro Model for Benchmarking Neuro-Inspired Architectures in Online Learning
2018 · Pai-Yu Chen, Xiaochen Peng, et al. · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · 653
Impact of Scaling on Neutron-Induced Soft Error in SRAMs From a 250 nm to a 22 nm Design Rule
2010 · Eishi Ibe, Hitoshi Taniguchi, et al. · IEEE Transactions on Electron Devices · 506
Modeling of failure probability and statistical design of SRAM array for yield enhancement in nanoscaled CMOS
2005 · S. Mukhopadhyay, H. Mahmoodi, et al. · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · 479
28nm FDSOI technology platform for high-speed low-voltage digital applications
2012 · N. Planes, O. Weber, et al. · Symposium on VLSI Technology · 461
NeuroSim+: An integrated device-to-algorithm framework for benchmarking synaptic devices and array architectures
2017 · Pai-Yu Chen, Xiaochen Peng, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 447
A 256-kb 65-nm Sub-threshold SRAM Design for Ultra-Low-Voltage Operation
2007 · Benton Highsmith Calhoun, Anantha P. Chandrakasan · IEEE Journal of Solid-State Circuits · 441
Single-event effects in avionics
1996 · E. Normand · IEEE Transactions on Nuclear Science · 421
CONV-SRAM: An Energy-Efficient SRAM With In-Memory Dot-Product Computation for Low-Power Convolutional Neural Networks
2018 · Avishek Biswas, Anantha P. Chandrakasan · IEEE Journal of Solid-State Circuits · 413
Compute-in-Memory Chips for Deep Learning: Recent Trends and Prospects
2021 · Shimeng Yu, Hongwu Jiang, et al. · IEEE Circuits and Systems Magazine · 391
Neural Cache: Bit-Serial In-Cache Acceleration of Deep Neural Networks
2018 · Charles Eckert, Xiaowei Wang, et al. · ACM/IEEE International Symposium on Computer Architecture (ISCA) · 375
DNN+NeuroSim: An End-to-End Benchmarking Framework for Compute-in-Memory Accelerators with Versatile Device Technologies
2019 · Xiaochen Peng, Shanshi Huang, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 366
3nm GAA Technology featuring Multi-Bridge-Channel FET for Low Power and High Performance Applications
2018 · Geumjong Bae, D.-I. Bae, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 366
Full copper wiring in a sub-0.25 μm CMOS ULSI technology
2002 · D. Edelstein, J. Heidenreich, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 358
A current-controlled latch sense amplifier and a static power-saving input buffer for low-power architecture
1993 · T. Kobayashi, K. Nogami, et al. · IEEE Journal of Solid-State Circuits · 349
Charge Pump Circuits: An Overview on Design Strategies and Topologies
2010 · Gaetano Palumbo, Domenico Pappalardo · IEEE Circuits and Systems Magazine · 339
An optimal memory allocation scheme for scratch-pad-based embedded systems
2002 · Oren Avissar, Rajeev Barua, et al. · ACM Transactions on Embedded Computing Systems · 325
DNN+NeuroSim V2.0: An End-to-End Benchmarking Framework for Compute-in-Memory Accelerators for On-Chip Training
2020 · Xiaochen Peng, Shanshi Huang, et al. · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · 311
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A 65 nm Sub-$V_{t}$ Microcontroller With Integrated SRAM and Switched Capacitor DC-DC Converter
2009 · Joyce Kwong, Yogesh K. Ramadass, et al. · IEEE Journal of Solid-State Circuits · 311
A 22nm SoC platform technology featuring 3-D tri-gate and high-k/metal gate, optimized for ultra low power, high performance and high density SoC applications
2012 · C.-H. Jan, U. Bhattacharya, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 310
Challenges and Trends of SRAM-Based Computing-In-Memory for AI Edge Devices
2021 · Chuan-Jia Jhang, Cheng-Xin Xue, et al. · IEEE Transactions on Circuits and Systems I Regular Papers · 294
Works count: 8,341
Citation count: 85,560
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