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Keyword

wirelength minimization

Description: Wirelength minimization is an optimization objective in very-large-scale integrated circuit design that reduces the total length of interconnects between components.
OpenAlex ID: keywords/wirelength-minimization
The Rectilinear Steiner Tree Problem is $NP$-Complete
1977 · M. R. Garey, D. S. Johnson · SIAM Journal on Applied Mathematics · 1,124
A Predictive Network Model of Cerebral Cortical Connectivity Based on a Distance Rule
2013 · Mária Ercsey-Ravasz, Nikola T. Markov, et al. · Neuron · 484
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A thermal-driven floorplanning algorithm for 3D ICs
2005 · J. Cong, Jie Wei, et al. · 431
Generic global placement and floorplanning
1998 · Hans Eisenmann, Frank M. Johannes · Proceedings - ACM IEEE Design Automation Conference · 397
The Backboard Wiring Problem: A Placement Algorithm
1961 · Leon Steinberg · SIAM Review · 379
Zero skew clock routing with minimum wirelength
1992 · Ting-Hai Chao, Yu-Chin Hsu, et al. · IEEE Transactions on Circuits and Systems II Analog and Digital Signal Processing · 352
Performance optimization of VLSI interconnect layout
1996 · Jason Cong, Lei He, et al. · Integration · 334
VTR 8
2020 · Kevin E. Murray, Oleg Petelin, et al. · ACM Transactions on Reconfigurable Technology and Systems · 300
Optimal Linear Ordering
1973 · D. Adolphson, T. C. Hu · SIAM Journal on Applied Mathematics · 275
Dragon2000: Standard-Cell Placement Tool For Large Industry Circuits
2000 · Maogang Wang, Xiaojian Yang, et al. · 261
Wafer-Scale Integration of Systolic Arrays
1985 · Leighton, Leiserson · IEEE Transactions on Computers · 246
Concepts of scale in simulated annealing
1984 · Steve R. White · AIP conference proceedings · 230
Zero-skew clock routing trees with minimum wirelength
2003 · K.D. Boese, A.B. Kahng · Annual IEEE International ASIC Conference and Exhibit · 220
A clustering-based optimization algorithm in zero-skew routings
1993 · Masato Edahiro · 220
A new class of iterative Steiner tree heuristics with good performance
1992 · A.B. Kahng, G. Robins · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · 215
FastPlace: efficient analytical placement using cell shifting, iterative local refinement,and a hybrid net model
2005 · N. Viswanathan, C.C.-N. Chu · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · 212
Multilevel generalized force-directed method for circuit placement
2005 · Tony Chan, Jason Cong, et al. · International Symposium on Physical Design · 204
A study of Through-Silicon-Via impact on the 3D stacked IC layout
2009 · Dae Hyun Kim, Krit Athikulwongse, et al. · 200
FastPlace 3.0: A Fast Multilevel Quadratic Placement Algorithm with Placement Congestion Control
2007 · Natarajan Viswanathan, Min Pan, et al. · Asia and South Pacific Design Automation Conference (ASP-DAC) · 200
Module Placement Based on Resistive Network Optimization
1984 · Chung-Kuan Cheng, E.S. Kuh · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · 194
Distributed genetic algorithms for the floorplan design problem
1991 · J.P. Cohoon, S.U. Hegde, et al. · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · 189
Performance-driven placement of cell based IC's
1989 · M. A. B. Jackson, E. S. Kuh · Proceedings - ACM IEEE Design Automation Conference · 182
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Interconnect and thermal-aware floorplanning for 3D microprocessors
2006 · W.-L. Hung, G.M. Link, et al. · International Symposium on Quality Electronic Design (ISQED) · 179
An efficient and effective detailed placement algorithm
2005 · Min Pan, N. Viswanathan, et al. · International Conference on Computer Aided Design · 176
Orientation Preference Patterns in Mammalian Visual Cortex
2001 · Alexei A. Koulakov, Dmitri B. Chklovskii · Neuron · 176
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Works count: 1,753
Citation count: 26,590
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