Work

Faster Arithmetic and Logical Unit CMOS Design with Reduced Number of Transistors

Year: 2011

Type: conference-paper

Source: Communications in computer and information science

DOI: 10.1007/978-3-642-19542-6_100

Authors: Rachit Patel, Harpreet Parashar, Mohd. Wajid

Institution: Jaypee University of Information Technology

Language: English

Topic: Low-power high-performance VLSI design

Subfield: Electrical and Electronic Engineering

Field: Engineering

Domain: Physical Sciences

Open Access status: closed

OpenAlex ID: W12469619

FWCI:

Cites: 5

Cited by: 7

Related to: 10