Timing issues in Cell Based VLSI design
Year: 1990
Type: dissertation
Abstract: With the advances in VLSI design, chip timing is becoming dominated by interconnect delays rather than macro performances. For many existing large computer circuits, the interconnect delays already account for more than a half of the clock cycle, and the portion of propagation time in the cycle continues to grow. Optimized for timing, some designs can permit a 25-35% increase in the clock rate without any changes in the logic or cell design. This fact requires a change in the approach to timing problems through the design process. This need is clearly understood by designers of supercomputers and many types of fast clock electronics.
In this dissertation, we present a new methodology and set of tools, which combine verification and predictive functions. In the proposed methodology, the physical design step is preceded with the timing analysis step. Timing analysis is augmented with predictive capabilities. During this step, the set of the most critical paths are predicted, and delay constraints on all the interconnects are computed.
First we demonstrate that existing methodologies of identification of the critical paths are deficient because they do not take into consideration many important characteristics of the design which influence performance. New criteria and a new methodology are proposed for the prediction of the critical paths prior to the physical design step. Second, we present several new polynomial zero-slack algorithms for the computation of timing constraints on all the interconnects. The new algorithms are based on the minimax idea to identify maximal delay bounds for nets, which will not violate the timing constraints on any of the logical paths in the design. Information about the critical paths and the delay bounds is supplied to the next physical step of the design so that the layout will meet the pre-stated timing requirements. Application of this new methodology to real designs is demonstrated.
DOI: 10.60713/pist-26033
Author: Youssef, H.
Institution: University of Minnesota
Language: English
Subfield: Electrical and Electronic Engineering
Field: Engineering
Domain: Physical Sciences
Open Access status: green
OpenAlex ID: W15130301