Year: 2012
Type: article
Abstract: As the demand for advanced packaging is growing, the value of mid-end process technologies is increasing in an effort to realize innovative device products. Substrate-free packaging and 3D integration are coming with the challenges to polymer resin deposition for interlayer dielectrics films and final passivation films and their developments of process integration. For cost reduction of Fan-out Wafer Level Packaging, we have demonstrated thick film deposition on square panel substrates using the photo-sensitive resin materials tailored to spray-coating and slit-coating. Chip stacking of a high performance logic chip on a high band-width DRAM needs fine pitch patterning of a thick photo-resist for Cu electroplated redistribution lines on the DRAM. Our successful process integration has confirmed that slight oxidation of the Cu seed surface to form Cu2O is preferred to improve adhesion between the resist and the Cu surface. Finally, the restoration of plasma damaged surface of a polymer final passivation film on advanced low-k chips to improve reliability of flip chip packages has been discussed as one of typical examples of materials design for process integration.
Authors: Hiroaki Ezawa, Masaya Shima, Tatsuo Migita, Soichi Homma, Masahiro Miyata
Institution: Toshiba (Japan)
Language: English
Topic: 3D IC and TSV technologies
Subfield: Electrical and Electronic Engineering
Field: Engineering
Domain: Physical Sciences
Open Access status: diamond
OpenAlex ID: W1963896342