Holographic memory design for a petaflop superconducting computer architecture
Year: 1998
Type: conference-paper
Abstract: We will descrihe the role of holographic memorv in a current research effort 1 that seeks to combine ariuus advanced technologies to achieve petaflops scale computing within the next decade In addition to holographic memory. the petatlop architecture combines superconductor Rapid Single Flu-.: Quantum (RSFQ) logic. which can operate at I 00 GHz within a cryogenic cm ironmem with power consumption less than 'iO watts. a packet-switching optical network with a multi-le el strncture capable of providing interconnection among tens or thousands of pons '' ith latencies of only I 0 to 30 nanoseconds. Processor-In-Memory (PIM) technology. and a multithreaded hierarchical structure (see Figure I) to allow the processors to access a high capacitv memnrv vhile compensating for the latenc)· problem inherent in such a system.
DOI: 10.1117/12.308959
Authors: Ernest Chuang, Wenhai Liu, Demetri Psaltis
Institution: California Institute of Technology
Language: English
Subfield: Atomic and Molecular Physics, and Optics
Field: Physics and Astronomy
Domain: Physical Sciences
Open Access status: green
OpenAlex ID: W1968170976