Work

A High Efficiency Active Rectifier for 6.78MHz Wireless Power Transfer Receiver with Bootstrapping Technique and All Digital Delay-Locked Loop

Year: 2014

Type: article

Abstract: This paper presents a new rectifier with a bootstrapping technique to reduce the effective drop voltage. An all-digital delay locked loop (ADDLL) circuit was also applied to prevent the reverse leakage current. The proposed rectifier uses NMOS diode connected instead of PMOS to reduce the design size and improve the frequency respond. All the sub-circuits of ADDLL were designed with low power consumption to reduce the total power of the rectifier. The rectifier was implemented in CMOS $0.35{\mu}m$ technology. The peak power conversion efficiency was 76 % at an input frequency of 6.78MHz and a power level of 5W.

Source: IEIE Transactions on Smart Processing and Computing

DOI: 10.5573/ieiespc.2014.3.6.410

Authors: Truong Thi Kim Nga, Hyung-Gu Park, Kang-Yoon Lee

Institution: Sungkyunkwan University

Language: English

Topic: Wireless Power Transfer Systems

Subfield: Electrical and Electronic Engineering

Field: Engineering

Domain: Physical Sciences

SDG: Industry, innovation and infrastructure

Open Access status: bronze

Funders: Ministry of Science, ICT and Future Planning, National IT Industry Promotion Agency, IC Design Education Center, Iran Telecommunication Research Center