Anytime System Level Verification via Random Exhaustive Hardware in the Loop Simulation
Year: 2014
Type: conference-paper
DOI: 10.1109/dsd.2014.91
Institution: Sapienza University of Rome
Language: English
Subfield: Computational Theory and Mathematics
Field: Computer Science
Domain: Physical Sciences
Open Access status: closed
Funder: Seventh Framework Programme
OpenAlex ID: W1978520001