Work

Loop nests parallelization for digital system synthesis

Year: 2013

Type: conference-paper

Source: IEEE East-West Design & Test Symposium (EWDTS)

DOI: 10.1109/ewdts.2013.6673180

Authors: Alexander Chemeris, Julia Gorunova, Dmiry Lazorenko

Institution: Pukhov Institute for Modelling in Energy Engineering

Language: English

Topic: Embedded Systems Design Techniques

Subfield: Hardware and Architecture

Field: Computer Science

Domain: Physical Sciences

Open Access status: closed

OpenAlex ID: W1985281137

FWCI:

Cites: 2

Cited by: 1

Related to: 10