Work

A New Efficient and Reliable Dynamically ReconfigurableNetwork-on-Chip

Year: 2012

Type: article

Abstract: We present a new reliableNetwork-on-Chip(NoC) suitable forDynamically Reconfigurable Multiprocessors on Chipsystems. The proposedNoCis based on routers performing online error detection of routing algorithm and data packet errors. Our work focuses on adaptive routing algorithms which allow to bypass faulty components or processor elements dynamically implemented inside the network. The proposed routing error detection mechanism allows to distinguish routing errors from bypasses of faulty components. The new router architecture is based on additional diagonal state indications and specific logic blocks allowing the reliable operation of theNoC. The main originality in the proposedNoCis that only the permanently faulty parts of the routers are disconnected. Therefore, our approach maintains a high run time throughput in theNoCwithout data packet loss thanks to a self‐loopbackmechanism inside each router.

Source: Journal of Electrical and Computer Engineering

DOI: 10.1155/2012/843239

Authors: Cédric Killian, Camel Tanougast, Fabrice Monteiro, Abbas Dandache

Institution: Université de Lorraine

Language: English

Topic: Interconnection Networks and Systems

Subfield: Computer Networks and Communications

Field: Computer Science

Domain: Physical Sciences

SDG: Industry, innovation and infrastructure

Open Access status: gold

Estimated APC paid: $571