Work

Chip Level Simulation of Substrate Noise Coupling and Interference in RF ICs with CMOS Digital Noise Emulator

Year: 2014

Type: article

Source: IEICE Transactions on Electronics

DOI: 10.1587/transele.e97.c.546

Authors: Naoya AZUMA, Shunsuke SHIMAZAKI, Noriyuki MIURA, Makoto NAGATA, Tomomitsu KITAMURA, Satoru TAKAHASHI, Motoki MURAKAMI, Kazuaki HORI, Atsushi NAKAMURA, Kenta TSUKAMOTO, Mizuki IWANAMI, Eiji HANKUI, Sho MUROGA, Yasushi ENDO, Satoshi TANAKA, Masahiro YAMAGUCHI

Institutions: Kobe University, Renesas Electronics (United States), Renesas Electronics (Japan), NEC (Japan), Tohoku University

Language: English

Topic: Radio Frequency Integrated Circuit Design

Subfield: Electrical and Electronic Engineering

Field: Engineering

Domain: Physical Sciences

Open Access status: closed

OpenAlex ID: W1995639733

FWCI:

Cites: 22

Cited by: 6

Related to: 10