Work

A 58mW 1.2mm2 HSDPA Turbo Decoder ASIC in 0.13μm CMOS

Year: 2008

Type: conference-paper

Abstract: This paper presents the implementation of the 1.2 mm2HSDPA turbo decoder ASIC in 0.13 mum CMOS achieves a measured maximum frequency of 246 MHz, which translates to a maximum throughput of 20.2 Mb/s at 5.5 iterations. The peak throughput of 10.8 Mb/s required for HSDPA is achieved at 58 mW and an energy efficiency of 0.7 nJ/b/iter. The number of iterations versus input SNR, as determined by the implemented stopping criterion, and corresponding power measurements.

Source: Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference

DOI: 10.1109/isscc.2008.4523158

Authors: Christian Benkeser, Andreas Burg, Teo Cupaiuolo, Qiuting Huang

Institution: ETH Zurich

Language: English

Topic: Error Correcting Code Techniques

Subfield: Computer Networks and Communications

Field: Computer Science

Domain: Physical Sciences

SDG: Industry, innovation and infrastructure

Open Access status: green

OpenAlex ID: W1997303236

FWCI: 1.227

Cites: 6

Cited by: 7

Related to: 10