Correction to “A 2 Gb/s Throughput CMOS Transceiver Chipset With In-Package Antenna for 60 GHz Short-Range Wireless Communication”
Year: 2013
Type: erratum
Abstract: The authors made an error in Fig. 19 in the above-named article [ibid., vol. 47, no. 12, pp. 3160–3171, Dec. 2012]. The figure is the same as Fig. 13 by mistake. The correct figure "Data rate/throughput measurement setup" is shown here. The authors apologize for any confusion.
Authors: Toshiya Mitomo, Yukako Tsutsumi, Hiroaki Hoshino, Masahiro Hosoya, Tong Wang, Yuta Tsubouchi, Ryoichi Tachibana, Akihide Sai, Yuka Kobayashi, Daisuke Kurose, Tomohiko Ito, Koichiro Ban, Tomoya Tandai, Takeshi Tomizawa
Institution: Toshiba (Japan)
Language: English
Subfield: Electrical and Electronic Engineering
Field: Engineering
Domain: Physical Sciences
Open Access status: bronze
OpenAlex ID: W2002122195