Year: 2014
Type: conference-paper
Abstract: With Moore’s law, critical dimensions (CD) become smaller and smaller, and CD control becomes a task of process developing and wafer fabrication. Gate shrinkage by wet process is one choice of non-lithography techniques to meet smaller CD requirements. In this paper, the polysilicon shrinkage amount can be adjusted by ionic surfactant ratio in TMAH (Tetra methyl ammonium hydroxide) and polysilicon with different phosphorous dopant dosage and thermal budget.
Source: ECS Transactions
Institutions: Powerchip (Taiwan), China University of Technology
Language: English
Subfield: Electrical and Electronic Engineering
Field: Engineering
Domain: Physical Sciences
Open Access status: bronze
OpenAlex ID: W2003451859