Year: 1983
Type: conference-abstract
Abstract: Direct-coupled FET logic (DCFL) circuits with self-aligned enhancement/depletion GaAs MESFETs are the most promising candidate for developing GaAs MSI/LSI circuits. A 4×4-bit parallel multiplier was fabricated as a test vehicle to demonstrate high-speed low-power circuit performance. The circuit chip measures 1.5 mm ×1.3 mm in size and contains 168 NOR gates with 2 µm gate length enhancement/depletion FETs. To evaluate the operating speed, a full adder implemented ring oscillator was fabricated. The propagation delay per gate was in the range between 210 and 260 ps with a power dissipation of 0.36 mW/gate. 4×4-bit multiplication was performed in 3.7 ns, with a power dissipation of 97 mW at a supply voltage of 1.5 V.
Authors: Katsuhiko Suyama, Haruo Shimizu, Shigeru Yokogawa, Yoshiro Nakayama, Akihiro Shibatomi
Institution: Fujitsu (Japan)
Language: English
Subfield: Electrical and Electronic Engineering
Field: Engineering
Domain: Physical Sciences
Open Access status: bronze
OpenAlex ID: W2005707061