Work

Managing annealing pattern effects in 45nm low power CMOS technology

Year: 2009

Type: conference-paper

Source: European Solid-State Device Research Conference

DOI: 10.1109/essderc.2009.5331536

Authors: P. Morin, F. Cacho, R. Beneyton, B. Dumont, M. Bidaud, E. Josse, C. Gallon, R. Ranica, A. Villaret, R. Bianchini, T. Devoivre, E. Serret, R. Binger, K. Barla, M. Haond, A. Colin, H. Bono, C. Chaton

Institutions: STMicroelectronics (France), Commissariat à l'Énergie Atomique et aux Énergies Alternatives, Laboratoire d'Électronique des Technologies de l'Information

Language: English

Topic: Advancements in Semiconductor Devices and Circuit Design

Subfield: Electrical and Electronic Engineering

Field: Engineering

Domain: Physical Sciences

Open Access status: closed

OpenAlex ID: W2006508798

FWCI: 0.937

Cites: 10

Cited by: 3

Related to: 10