Work

A 10-bit 300MSample/s pipelined ADC using time-interleaved SAR ADC for front-end stages

Year: 2010

Type: conference-paper

Source: IEEE International Symposium on Circuits and Systems proceedings

DOI: 10.1109/iscas.2010.5537646

Authors: Young-Hwa Kim, Jaewon Lee, SeongHwan Cho

Institution: Korea Advanced Institute of Science and Technology

Language: English

Topic: Analog and Mixed-Signal Circuit Design

Subfield: Electrical and Electronic Engineering

Field: Engineering

Domain: Physical Sciences

Open Access status: closed

Funder: Electronics and Telecommunications Research Institute

OpenAlex ID: W2007246491

FWCI: 2.567

Cites: 8

Cited by: 12

Related to: 10