Interconnect Scaling Scenario Using A Chip Level Interconnect Model
Year: 1997
Type: conference-paper
Source: Symposium on VLSI Technology
Authors: Yamashita, Odanaka
Institution: Panasonic (Japan)
Language: English
Subfield: Computer Networks and Communications
Field: Computer Science
Domain: Physical Sciences
Open Access status: closed
OpenAlex ID: W2015949508