Design innovations to optimize the 3D stackable vertical gate (VG) NAND flash
Year: 2012
Type: conference-paper
Authors: Chun-Hsiung Hung, Hang-Ting Lue, Shuo-Nan Hung, Chih-Chang Hsieh, Kuo-Pin Chang, Ti-Wen Chen, Shih-Lin Huang, Tzung Shen Chen, Chih-Shen Chang, Wen-Wei Yeh, Yi-Hsuan Hsiao, Chieh-Fang Chen, Shih-Cheng Huang, Yan-Ru Chen, Guan-Ru Lee, Chih-Wei Hu, Shih-Hung Chen, Chia-Jung Chiu, Yen-Hao Shih, Chih-Yuan Lu
Institution: Macronix International (Taiwan)
Language: English
Subfield: Electrical and Electronic Engineering
Field: Engineering
Domain: Physical Sciences
Open Access status: closed
OpenAlex ID: W2018174035