A Layout System for the Random Logic Portion of an MOS LSI Chip
Year: 1981
Type: article
Source: IEEE Transactions on Computers
Authors: Shirakawa, Okuda, Harada, Tani, Ozaki
Institutions: The University of Osaka, Sharp Corporation (Japan), NEC (Japan)
Language: English
Subfield: Electrical and Electronic Engineering
Field: Engineering
Domain: Physical Sciences
Open Access status: closed
OpenAlex ID: W2019017708